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US 2010/0306301 A1Published application
Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor
AssigneeAdvanced Micro Devices, Inc.
InventorsKevin A. Hurd, Scott A. Hilker
Life of this patent
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Abstract
Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.
Claims20
A multiplier-adder comprising:
- a multiplier having first and second inputs for receiving first and second operands, a first output for providing a sum signal, and a second output for providing a carry signal;
- a biased addend generator having first and second inputs for receiving sign bits of said first and second operands, a third input for receiving a third operand, a first output for providing a biased addend signal, and a second output for providing a signal representative of a sign of a product of said first and second operands;
- an adder having first and second inputs coupled to said first and second outputs of said multiplier, a third input for receiving said biased addend signal, and an output for providing a signal representative of a sum of said first, second, and third inputs;
- a multiplexer having a first input coupled to said first output of said adder, a second input for receiving a saturated minimum value, a third input for receiving a saturated maximum value, a control input, and an output for providing a multiply-add result with saturation signal;
- and
- select logic having a first input coupled to said second output of said bias generator and a second input for receiving a signal representative of a sign of said sum, and an output coupled to said control input of said multiplexer.
3 more elements
An arithmetic processing unit comprising:
- a multiplier for providing sum and carry signals representing a product of first and second operands;
- an adder for providing an intermediate result signal representative of a sum of said sum signal, said carry signal, and a bias signal;
- a bias generator for providing said bias signal having a value determined by a sign of a product of said first and second operands;
- and
- output selection circuitry for selecting one of a portion of said first output signal of said adder, a saturated minimum value, and a saturated maximum value in response to said sign of said product and a sign of said intermediate result.
2 more elements
A method comprising:
- forming sum and carry signals representing a product of first and second operands;
- forming a bias signal having a value determined by a sign of a product of said first and second operands;
- providing a first output signal in response to an addition of said sum signal, said carry signal, a sign-extended addend, and said bias signal;
- and
- selecting one of a portion of said first output signal, a saturated minimum value, and a saturated maximum value, as a final result in response to said sign of said product and a sign of said first output signal.
2 more elements
Dependencies are inferred from the claim text.