Galois Field Multiplier

Abstract

A Galois field multiplier is provided, comprising a multiplication circuit for inputting two m bits binary multiplicators and outputting their product, wherein m is an integral power of 2, and the output of said multiplication circuit is consisted of a high bits portion output and a low bits portion output; a memory for storing a Galois field multiplication coefficient array calculated from a selected Galois field primitive polynomial; a first module for performing operation on the output of said multiplication circuit and the Galois field multiplication coefficient array stored in said memory to obtain the product of the two m bits binary multiplicators over Galois field. The Galois field multiplier has small hardware footprint, short response latency and strong universality.

Dependencies are inferred from the claim text.