DSP Engine with Implicit Mixed Sign Operands
AssigneeMicrochip Technology Incorporated
InventorsMichael I. Catherwood, Settu Duraisamy
Life of this patent
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Abstract
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.
Claims29
A processor, comprising:
- at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode;
- a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.
A method for performing a multiplication in a processor comprising the steps of
- providing a first n-bit operand from a first location to a multiplier unit, wherein the multiplier unit can be controlled to operate in signed, unsigned, or a combined sign/unsigned mode;
- providing a second operand from a second location to the multiplier unit;
- decoding the location for the first and second operand and controlling the multiplier unit to operate in a mixed mode in which a signed, an unsigned, or a combined sign/unsigned multiplication is performed depending on the locations.
A method for performing a 2n-bit multiplication using 4 n-bit data words, comprising the steps of:
- storing a first operand of the 2n-bit multiplication in a first set of two consecutive registers or two consecutive memory locations;
- storing a second operand of the 2n-bit multiplication in a second set of two consecutive registers or two consecutive memory addresses;
- performing a first multiplication by a controllable multiplier unit using a first register or memory address of the first set and a first register or memory address of the second set and shifting an associated first result,
- performing a second multiplication by the controllable multiplier unit using the first register or memory address of the first set and a second register or memory address of the second set to generate an associated second result,
- performing a third multiplication by the controllable multiplier unit using the first register or memory address of the second set and a second register or memory address of the first set to generate an associated third result,
- wherein for each multiplication, the multiplier unit is automatically controlled to operate in signed, unsigned, or a combined sign/unsigned mode depending on the location of the register or address;
- adding the first, second and third result to generate an end result and storing the end result in registers or memory.
Dependencies are inferred from the claim text.