Selective local interconnect to gate in a self aligned local interconnect process
AssigneeAdvanced Micro Devices, Inc.
InventorRichard T. Schultz
Life of this patent
Estimating the term…
Abstract
A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.
Claims21
A semiconductor device fabrication process, comprising:
- selectively removing a hard mask in one or more selected regions over a gate of a transistor on a semiconductor substrate, wherein removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor;
- and
- depositing conductive material in one or more trenches formed through the at least one insulating layer, wherein the conductive material forms a local interconnect to the gate in at least one of the selected regions.
A semiconductor device fabrication process, comprising:
- forming a gate of a transistor on a semiconductor substrate using a hard mask;
- placing a gate hard mask etch pattern over the transistor;
- selectively removing the hard mask in one or more selected regions over the gate using the gate hard mask etch pattern;
- forming one or more insulating layers over the transistor;
- forming a trench through at least one of the insulating layers in at least one of the selected regions over the gate such that the gate is exposed in the trench;
- and
- depositing conductive material in the trench, wherein the conductive material forms a local interconnect to the gate in at least one of the selected regions.
A semiconductor device fabrication process, comprising:
- forming a gate of a transistor on a semiconductor substrate using a hard mask;
- forming one or more insulating layers over the transistor;
- forming a trench through at least one of the insulating layers in at least one of the selected regions over the gate such that the gate and the hard mask are exposed in the trench;
- placing a gate hard mask etch pattern over the transistor;
- selectively removing the hard mask in the selected regions over the gate using the gate hard mask etch pattern;
- and
- depositing conductive material in the trench, wherein the conductive material forms a local interconnect to the gate in at least one of the selected regions.
A computer readable storage medium storing a plurality of instructions which, when executed, generate one or more resist patterns useable in a semiconductor process that comprises:
- selectively removing a hard mask in one or more selected regions over a gate of a transistor on a semiconductor substrate, wherein removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor;
- and
- depositing conductive material in one or more trenches formed through the at least one insulating layer, wherein the conductive material forms a local interconnect to the gate in at least one of the selected regions.
Dependencies are inferred from the claim text.