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US 2010/0304540 A1Published application
Semiconductor device and method of forming the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Sung-Taeg Kang
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Abstract
There is provided a semiconductor device and a method of forming the same. The semiconductor device includes a memory device and a self-aligned selection device. A floating junction is formed between the self-aligned selection device and the memory device.
Claims16
A method of forming a semiconductor device, comprising:
- forming a first conductive layer pattern on a substrate;
- forming a stacked pattern including an inter-gate insulation layer pattern and a second conductive layer pattern on the first conductive layer pattern;
- forming a mask insulation layer pattern on the first conductive layer pattern spaced apart from the stacked pattern;
- removing the first conductive layer pattern outside the stacked pattern and the mask insulation layer pattern to form a floating gate below the stacked pattern, and to form a selection gate below the mask insulation layer pattern;
- forming a floating junction on the substrate between the floating gate and the selection gate;
- and
- forming a spacer on one sidewall of the stacked pattern adjacent to the selection gate after the forming of the floating junction,
- wherein the spacer completely covers the floating junction between the floating gate and the selection gate, and extends toward a sidewall of the selection gate.
5 more elements
A method of forming a semiconductor device, comprising:
- forming a conductive layer pattern on a substrate;
- forming a stacked pattern including an inter-layer insulation layer and a control gate on the conductive layer pattern;
- forming a spacer on at least one sidewall of the stacked pattern;
- forming a mask insulation layer pattern on the conductive layer pattern exposed outside of the spacer;
- removing the spacer;
- etching the conductive layer pattern outside the stacked pattern to form a floating gate below the stacked pattern and to form a selection gate below the mask insulation layer pattern;
- performing a first ion implantation process to form a floating junction on a substrate between the floating gate and the selection gate;
- and
- performing a second ion implantation process to form a source and a drain on the substrate outside the floating gate and the selection gate not adjacent to the floating junction.
6 more elements
Dependencies are inferred from the claim text.