Method of manufacturing layered chip package

A method of manufacturing a layered chip package, the layered chip package comprising:

• a main body having a top surface, a bottom surface and four side surfaces;
• and
• wiring disposed on at least one of the side surfaces of the main body, wherein:
• the main body includes a plurality of layer portions stacked;
• each of the plurality of layer portions includes:
• a semiconductor chip having a first surface with a device formed thereon, a second surface opposite to the first surface, and four side surfaces;
• an insulating portion covering at least one of the four side surfaces of the semiconductor chip;
• and a plurality of electrodes connected to the semiconductor chip;
• the insulating portion has at least one end face located at the at least one of the side surfaces of the main body on which the wiring is disposed;
• each of the plurality of electrodes has an end face that is surrounded by the insulating portion and located at the at least one of the side surfaces of the main body on which the wiring is disposed;
• the wiring is connected to the end faces of the plurality of electrodes of the plurality of layer portions;
• and
• the plurality of layer portions include at least a pair of layer portions that are disposed such that the first surfaces of the respective semiconductor chips face toward each other,
• the method comprising the steps of:
• fabricating a layered substructure by stacking a plurality of substructures in correspondence with the order of stacking of the plurality of layer portions of the layered chip package, wherein the plurality of substructures respectively correspond to the plurality of layer portions of the layered chip package, each substructure including a plurality of its corresponding layer portions and being intended to be cut later at a boundary between every adjacent ones of the plurality of its corresponding layer portions;
• and
• fabricating a plurality of layered chip packages by using the layered substructure,
• wherein the step of fabricating the layered substructure includes the steps of:
• fabricating a first pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the first pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned;
• fabricating a second pre-substructure wafer by performing processing on a first surface of a semiconductor wafer having the first surface and a second surface that face toward opposite directions, the second pre-substructure wafer having a first surface and a second surface that respectively correspond to the first surface and the second surface of the semiconductor wafer and including a plurality of pre-semiconductor-chip portions aligned;
• fabricating a first pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the first pre-substructure wafer, wherein the first pre-polishing substructure is fabricated through:
• forming in the first pre-substructure wafer at least one groove that extends to be adjacent to at least one of the pre-semiconductor-chip portions, the at least one groove opening at the first surface of the first pre-substructure wafer and having a bottom that does not reach the second surface of the first pre-substructure wafer;
• forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later;
• and forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer;
• fabricating a second pre-polishing substructure having a first surface and a second surface that respectively correspond to the first surface and the second surface of the second pre-substructure wafer, wherein the second pre-polishing substructure is fabricated through:
• forming in the second pre-substructure wafer at least one groove that extends to be adjacent to at least one of the pre-semiconductor-chip portions, the at least one groove opening at the first surface of the second pre-substructure wafer and having a bottom that does not reach the second surface of the second pre-substructure wafer;
• forming an insulating layer to fill the at least one groove, the insulating layer being intended to become part of the insulating portion later;
• and forming the plurality of electrodes such that part of each of the electrodes lies on the insulating layer;
• bonding the first and second pre-polishing substructures to each other such that the respective first surfaces of the first and second pre-polishing substructures face toward each other;
• and
• polishing the respective second surfaces of the first and second pre-polishing substructures in a bonded state so as to obtain a stack of a first substructure and a second substructure, the first substructure being formed by thinning the first pre-polishing substructure by the polishing, the second substructure being formed by thinning the second pre-polishing substructure by the polishing.