Fabricating method of thin film transistor array substrate

A fabricating method of a thin film transistor array substrate, comprising:

• providing a substrate, wherein the substrate has a pixel region and a bonding pad region located surrounding the pixel region;
• forming a patterned polysilicon layer within the pixel region on the substrate, wherein the patterned polysilicon layer comprises a source and a drain;
• forming a first patterned insulating layer to cover the patterned polysilicon layer;
• forming a first patterned transparent conductive layer on the first patterned insulating layer;
• forming a first metal layer on the first patterned transparent conductive layer, wherein the first metal layer is partially disposed on the first patterned transparent conductive layer and comprises a gate, a scan line electrically connected to the gate and a common line disposed within the pixel region, and a part of the first patterned transparent conductive layer is disposed under the common line;
• forming a second patterned insulating layer to cover the first metal layer, wherein the first patterned insulating layer and the second patterned insulating layer have a first contact hole to expose the drain;
• forming a second patterned transparent conductive layer on the second patterned insulating layer, wherein a part of the second patterned transparent conductive layer is electrically connected to the drain via the first contact hole;
• forming a second metal layer on the second patterned transparent conductive layer, wherein the second metal layer is partially disposed on the second patterned transparent conductive layer and the second metal layer comprises a data line electrically connected to the source, and a part of the second patterned transparent conductive layer is disposed under the data line;
• forming a third patterned insulating layer to cover the second metal layer, wherein the third patterned insulating layer has a second contact hole to expose the second patterned transparent conductive layer electrically connected to the drain;
• and
• forming a third patterned transparent conductive layer on the third patterned insulating layer, wherein the third patterned transparent conductive layer comprises a pixel electrode located within the pixel region, and the pixel electrode is electrically connected to the second patterned transparent conductive layer via the second contact hole.