Fabrication method of semiconductor integrated circuit device

A method of manufacturing a semiconductor integrated circuit device, comprising the steps of:

• (a) providing a semiconductor wafer which has a plurality of chip regions each having a semiconductor integrated circuit formed thereon and each having a plurality of first electrodes electrically connected to the semiconductor integrated circuit;
• (b) preparing a first card comprising a wiring substrate having first interconnects formed thereon, a first sheet having a plurality of contact terminals to be brought into contact with the first electrodes and a pressing mechanism arranged over a region of the first sheet in which the plurality of contact terminals are formed,
• the first sheet including a first insulating film, a plurality of second interconnects formed over a upper surface of the first insulating film, a second insulating film formed over the plurality of second interconnects, and a second insulating film formed over the plurality of second interconnects,
• a second sheet formed over the second insulating film and arranged over the region of the first sheet in which the plurality of contact terminals are formed,
• the second sheet having first openings,
• elastic materials formed in the first openings,
• the plurality of contact terminals being formed at a lower surface of the first insulating film,
• the plurality of second interconnects being electrically connected to the plurality of contact terminals and to the first interconnects,
• the pressing mechanism having a plate form and arranged over the second sheet and the elastic materials such that the pressing mechanism is in contact with the elastic materials,
• wherein the second sheet is comprised of a metal sheet and has a linear expansion coefficient close to that of the semiconductor wafer;
• and
• (c) bringing tip portions of the contact terminals into contact with the first electrodes of the semiconductor wafer by pressing the first sheet with the pressing mechanism for performing electrical testing of the semiconductor integrated circuit,
• wherein each of the tip portions of the contact terminals is disposed over a corresponding one of the first electrodes.