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US 2010/0303375 A1Published application
Image processing apparatus
AssigneeKabushiki Kaisha Toshiba
InventorsTakahiro Suzuki, Masahiko Kato
Life of this patent
Estimating the term…
Abstract
An image quality adjusting circuit in an image processing apparatus is provided with a line memory unit, a delay circuit unit, a first to fourth filter processing circuits, and an adder. In the delay circuit unit, delay circuits are arranged in a matrix form. Delay circuits arranged in a horizontal direction receive an image data directly or via line memories. The image quality adjusting circuit each perform filter processing on the received image data signals lying in a horizontal direction, in a vertical direction, in a down-right direction, and in a down-left direction. The image quality adjusting circuit performs addition of the image data on a focus pixel and the filter-processed data, and thus performs edge correction processing.
Claims16
An image processing apparatus comprising:
- a delay circuit unit to receive image signals directly or via line memories, the delay circuit unit having delay circuits arranged in an m×n matrix form (where m and n are integers not less than 3);
- a first filter processing circuit to receive image data signals lying in a horizontal direction of the delay circuit unit, and to generate a first filter processing signal by performing filter processing on the received image data lying in the horizontal direction;
- a second filter processing circuit to receive image data signals lying in a vertical direction of the delay circuit unit, and to generate a second filter processing signal by performing filter processing on the received image data lying in the vertical direction;
- a third filter processing circuit to receive image data signals lying in a down-right direction of the delay circuit unit, and to generate a third filter processing signal by performing filter processing on the received image data lying in the down-right direction;
- and
- a fourth filter processing circuit to receive image data signals lying in a down-left direction of the delay circuit unit, and to generate a fourth filter processing signal by performing filter processing on the received image data lying in the down-left direction.
3 more elements
An image processing apparatus comprising:
- a delay circuit unit to receive image signals directly or via line memories, the delay circuit unit having delay circuits arranged in an m×n matrix form (where m and n are integers not less than 3);
- a first filter processing circuit to receive image data signals lying in a horizontal direction of the delay circuit unit, and to generate a first filter processing signal by performing filter processing on the received image data lying in the horizontal direction;
- a second filter processing circuit to receive image data signals lying in a vertical direction of the delay circuit unit, and to generate a second filter processing signal by performing filter processing on the received image data lying in the vertical direction;
- a third filter processing circuit to receive image data signals lying in a down-right direction of the delay circuit unit, and to generate a third filter processing signal by performing filter processing on the received image data lying in the down-right direction;
- a fourth filter processing circuit to receive image data signals lying in a down-left direction of the delay circuit unit, and to generate a fourth filter processing signal by performing filter processing on the received image data lying in the down-left direction;
- a first nonlinear processing circuit to receive a first image data signal, which is of image data on a focus pixel of the delay circuit unit, and to generate a first nonlinear processing signal;
- a second nonlinear processing circuit to receive the first image data signal and the second filter processing signal, and to generate a second nonlinear processing signal;
- a third nonlinear processing circuit to receive the first image data signal and the third filter processing signal, and to generate a third nonlinear processing signal;
- a fourth nonlinear processing circuit to receive the first image data signal and the fourth filter processing signal, and to generate a fourth nonlinear processing signal;
- and
- an adder to receive the first image data and the first to fourth nonlinear processing signals, and to perform addition of the first image data and the first to fourth nonlinear processing signals.
8 more elements
An image processing apparatus comprising:
- a delay circuit unit to receive image signals directly or via line memories, the delay circuit unit having delay circuits arranged in an m×n matrix form (where m and n are integers not less than 3);
- a first filter processing circuit to receive image data signals lying in a horizontal direction of the delay circuit unit, and to generate a first filter processing signal by performing filter processing on the received image data lying in the horizontal direction;
- a second filter processing circuit to receive image data signals lying in a vertical direction of the delay circuit unit, and to generate a second filter processing signal by performing filter processing on the received image data lying in the vertical direction;
- a third filter processing circuit to receive image data signals lying in a down-right direction of the delay circuit unit, and to generate a third filter processing signal by performing filter processing on the received image data lying in the down-right direction;
- a fourth filter processing circuit to receive image data signals lying in a down-left direction of the delay circuit unit, and to generate a fourth filter processing signal by performing filter processing on the received image data lying in the down-left direction;
- a first adder to receive the first to fourth filter processing signals, and to generate an addition processing signal by performing addition of the filter-processed image data in the horizontal direction, the filter-processed image data in the vertical direction, the filter-processed image data in the down-right direction, and the filter-processed image data in the down-left direction;
- a nonlinear processing circuit to receive a first image data signal, which is image data on a focus pixel of the delay circuit unit, and the addition processing signal, and to generate a coring-processed nonlinear processing signal by
- generating a constant coring value which stays constant in an area where a luminance value of the first image data signal is not less than a first predetermined value and also generating a variable coring value which varies in another area where the luminance value of the first image data signal is not more than the first predetermined value, the variable coring value increasing as the luminance value of the first image data signal decreases so as to be larger than the constant coring value, and
- performing coring processing on the addition-processed image data with the generated coring value;
- and
- a second adder to receive the first image data signal and the nonlinear processing signal, and to generate an enhancement-processed image by performing addition of the image data on the focus pixel of the delay circuit unit and the coring-processed image data.
8 more elements
Dependencies are inferred from the claim text.