Synchronization circuit, synchronization method, and reception system

A synchronization method comprising the steps of:

• based on a received signal being input, causing a first phase-locked loop circuit to output a first phase control signal representing a phase control amount of said received signal;
• given the same input received signal as that input to said first phase-locked loop circuit, causing a second phase-locked loop circuit to output a second phase control signal representing a phase control amount of said received signal;
• causing a first output circuit to control the phase of said received signal based on said first phase control signal in order to output a phase-controlled signal;
• causing a second output circuit to control the phase of said received signal based on said second phase control signal in order to output a phase-controlled signal;
• causing a first detection circuit to detect a phase control error of said first phase-locked loop circuit based on the phase-controlled signal output from said first output circuit;
• causing a second detection circuit to detect a phase control error of said second phase-locked loop circuit based on the phase-controlled signal output from said second output circuit;
• and
• if the phase control error of said first phase-locked loop circuit detected by said first detection circuit is larger than the phase control error of said second phase-locked loop circuit detected by said second detection circuit, then setting the loop gain of a first loop filter included in said first phase-locked loop circuit to be the same as the loop gain of a second loop filter included in said second phase-locked loop circuit.

A reception system comprising:

• acquisition means for acquiring a signal transmitted over a transmission channel;
• and
• transmission channel decode processing means for performing processing including a synchronous detection process on the signal acquired by said acquisition means;
• wherein said transmission channel decode processing means includes
• a first phase-locked loop circuit configured to output, based on a received signal being input, a first phase control signal representing a phase control amount of said received signal,
• a second phase-locked loop circuit configured to output, given the same input received signal as that input to said first phase-locked loop circuit, a second phase control signal representing a phase control amount of said received signal,
• a first output circuit configured to control the phase of said received signal based on said first phase control signal in order to output a phase-controlled signal,
• a second output circuit configured to control the phase of said received signal based on said second phase control signal in order to output a phase-controlled signal,
• a first detection circuit configured to detect a phase control error of said first phase-locked loop circuit based on the phase-controlled signal output from said first output circuit,
• a second detection circuit configured to detect a phase control error of said second phase-locked loop circuit based on the phase-controlled signal output from said second output circuit, and
• a control circuit configured such that if the phase control error of said first phase-locked loop circuit detected by said first detection circuit is larger than the phase control error of said second phase-locked loop circuit detected by said second detection circuit, then said control circuit sets the loop gain of a first loop filter included in said first phase-locked loop circuit to be the same as the loop gain of a second loop filter included in said second phase-locked loop circuit.

A reception system comprising:

• transmission channel decode processing means for performing processing including a synchronous detection process on a signal acquired over a transmission channel;
• and
• information source decode processing means for decoding data targeted to be transmitted from the signal processed by said transmission channel decode processing means;
• wherein said transmission channel decode processing means includes
• a first phase-locked loop circuit configured to output, based on a received signal being input, a first phase control signal representing a phase control amount of said received signal,
• a second phase-locked loop circuit configured to output, given the same input received signal as that input to said first phase-locked loop circuit, a second phase control signal representing a phase control amount of said received signal,
• a first output circuit configured to control the phase of said received signal based on said first phase control signal in order to output a phase-controlled signal,
• a second output circuit configured to control the phase of said received signal based on said second phase control signal in order to output a phase-controlled signal,
• a first detection circuit configured to detect a phase control error of said first phase-locked loop circuit based on the phase-controlled signal output from said first output circuit,
• a second detection circuit configured to detect a phase control error of said second phase-locked loop circuit based on the phase-controlled signal output from said second output circuit, and
• a control circuit configured such that if the phase control error of said first phase-locked loop circuit detected by said first detection circuit is larger than the phase control error of said second phase-locked loop circuit detected by said second detection circuit, then said control circuit sets the loop gain of a first loop filter included in said first phase-locked loop circuit to be the same as the loop gain of a second loop filter included in said second phase-locked loop circuit.

A reception system comprising:

• transmission channel decode processing means for performing processing including a synchronous detection process on a signal acquired over a transmission channel;
• and
• output means for outputting an image or a sound based on the signal processed by said transmission channel decode processing means;
• wherein said transmission channel decode processing means includes
• a first phase-locked loop circuit configured to output, based on a received signal being input, a first phase control signal representing a phase control amount of said received signal,
• a second phase-locked loop circuit configured to output, given the same input received signal as that input to said first phase-locked loop circuit, a second phase control signal representing a phase control amount of said received signal,
• a first output circuit configured to control the phase of said received signal based on said first phase control signal in order to output a phase-controlled signal,
• a second output circuit configured to control the phase of said received signal based on said second phase control signal in order to output a phase-controlled signal,
• a first detection circuit configured to detect a phase control error of said first phase-locked loop circuit based on the phase-controlled signal output from said first output circuit,
• a second detection circuit configured to detect a phase control error of said second phase-locked loop circuit based on the phase-controlled signal output from said second output circuit, and
• a control circuit configured such that if the phase control error of said first phase-locked loop circuit detected by said first detection circuit is larger than the phase control error of said second phase-locked loop circuit detected by said second detection circuit, then said control circuit sets the loop gain of a first loop filter included in said first phase-locked loop circuit to be the same as the loop gain of a second loop filter included in said second phase-locked loop circuit.

A reception system comprising:

• transmission channel decode processing means for performing processing including a synchronous detection process on a signal acquired over a transmission channel;
• and
• recording means for recording the signal processed by said transmission channel decode processing means;
• wherein said transmission channel decode processing means includes
• a first phase-locked loop circuit configured to output, based on a received signal being input, a first phase control signal representing a phase control amount of said received signal,
• a second phase-locked loop circuit configured to output, given the same input received signal as that input to said first phase-locked loop circuit, a second phase control signal representing a phase control amount of said received signal,
• a first output circuit configured to control the phase of said received signal based on said first phase control signal in order to output a phase-controlled signal,
• a second output circuit configured to control the phase of said received signal based on said second phase control signal in order to output a phase-controlled signal,
• a first detection circuit configured to detect a phase control error of said first phase-locked loop circuit based on the phase-controlled signal output from said first output circuit,
• a second detection circuit configured to detect a phase control error of said second phase-locked loop circuit based on the phase-controlled signal output from said second output circuit, and
• a control circuit configured such that if the phase control error of said first phase-locked loop circuit detected by said first detection circuit is larger than the phase control error of said second phase-locked loop circuit detected by said second detection circuit, then said control circuit sets the loop gain of a first loop filter included in said first phase-locked loop circuit to be the same as the loop gain of a second loop filter included in said second phase-locked loop scircuit.