Method and Apparatus for Providing Precise Transport Stream Packet Ordering and Erasure Optimization for Digital Video Decoder

A method comprising:

• receiving a plurality of transport steam packets, said transport stream packets encapsulating at least one multi-protocol encapsulation (MPE) packet including an MPE packet header, said multi-protocol encapsulation packet further encapsulating a plurality of Internet Protocol (IP) datagrams, wherein said MPE packet is received in an MPE frame that includes forward error correction (FEC) data for said MPE packet;
• decoding the plurality of transport stream packets by packet decoding logic and obtaining a decoding failure;
• marking all bytes of said MPE packet including said MPE packet header as erasures;
• and
• introducing said erasures to an erasure based decoder along with a plurality of successfully decoded MPE packets.

A method comprising:

• receiving a portion of a multi-protocol encapsulation (MPE) forward error correction (FEC) MPE-FEC table, via a plurality of transport steam packets, said transport stream packets encapsulating at least one MPE packet including an MPE packet header, said MPE packet further encapsulating a plurality of Internet Protocol (IP) datagrams;
• determining by packet decoding logic that an error is possible in the MPE-FEC table;
• designating an area of said MPE-FEC table as an area of suspicion and marking all bytes in said area of suspicion as erasures;
• introducing said erasures to a simplified erasure-based Reed-Solomon (ERS) decoder logic including a Syndrome Calculation Unit and an Error Correlation Unit, but not including a Key Equation Solver and a Chien Search Unit;
• and
• decoding, using said simplified ERS decoder logic, said erasures along with a remainder of said MPE-FEC table.

An apparatus comprising:

• a multi-protocol encapsulation forward error correction (MFEC) logic;
• a lost packet determination logic, operatively coupled to said MFEC logic, said lost packet determination logic operative to:
• estimate an expected number of packets, expected to be received within a time interval, based on packet arrival speed;
• and
• determine a number of lost packets using the expected number of packets and a packet counter wherein the packet counter counts a plurality of received packets.

A computer readable memory comprising:

• executable instructions for execution by at least one processor, that when executed cause said at least one processor to:
• estimate an expected number of packets, expected to be received within a time interval, based on packet arrival speed;
• and
• determine a number of lost packets, by said lost packet determination logic, using the expected number of packets and a packet counter wherein the packet counter counts a plurality of received packets.