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US 2010/0303067 A1Published application
Asynchronous pipielined interconnect architecture with fanout support
AssigneeAchronix Semiconductor Corporation
InventorsRajit Manohar, Clinton W. Kelly, Virantha Ekanayake
Life of this patent
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Abstract
Circuits comprising an asynchronous programmable interconnect with fan out support that include a multi-port switch and a first and second buffer-switch circuit, and methods of forming such circuits, are provided. Additional circuits and methods are disclosed.
Claims26
A circuit comprising:
- a multi-port switch point comprising a plurality of ports and a first buffer-switch circuit, the first buffer-switch circuit to provide a first set of programmable asynchronous connections between all ports of the plurality of ports, the programmable asynchronous connections to transmit data and control signals, the first buffer-switch circuit to fan out multiple control signals.
A circuit comprising:
- a multi-port switch point comprising a plurality of ports and a first buffer-switch circuit, the first buffer-switch circuit to provide a first set of programmable asynchronous connections between a selected number of the plurality of ports.
A method comprising:
- forming a multi-port switch point comprising a plurality of ports and a first buffer-switch circuit, the first buffer-switch circuit to provide a first set of programmable asynchronous connections between all ports of the plurality of ports;
- the first buffer-switch circuit to fan out multiple control signals.
A method comprising:
- forming a multi-port switch comprising a plurality of ports and a first buffer-switch circuit, the first buffer-switch circuit to provide a first set of programmable asynchronous connections between a selected number of the plurality of ports.
An asynchronous integrated circuit comprising:
- a plurality of logic blocks;
- a plurality of tracks to interconnect the logic blocks;
- and
- a plurality of multi-port switches, each multi-port switch point being formed at an intersection of two of the plurality of tracks and comprising a plurality of ports and at least a buffer-switch circuit, the buffer-switch circuit to provide a set of programmable asynchronous connections between all ports of the plurality of ports, the programmable asynchronous connections being used to transmit data and control signals, the buffer-switch circuit comprising a programmable completion detection element to fan out multiple control signals.
1 more element
Dependencies are inferred from the claim text.