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US 2010/0302894 A1Published application
Word line selection circuit and row decoder
AssigneeNEC Electronics Corporation
InventorsHiroyuki Takahashi, Masahiro Yoshida, Noriaki Takeda
Life of this patent
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Abstract
A first exemplary aspect of the present invention is a word line selection circuit where address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and that a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.
Claims12
A word line selection circuit wherein
- address decode signals composed of a power supply voltage and a first voltage lower than a ground voltage are input, and
- a word line selection signal composed of the first voltage and a second voltage higher than the power supply voltage is output not via a level shift circuit according to the address decode signals.
A word line selection circuit comprising:
- an inverter circuit that drives a boosted power supply potential VPP as a power supply, an output node of the inverter circuit being connected to a word line;
- and
- a final stage row decoder that has a control output node output-wired to an input node of the inverter circuit, and that changes a potential of the control output node based on a result of having decoded groups of address control signals from a preceding stage row decoder, wherein
- the final stage row decoder is provided with variable resistance means between the boosted power supply potential VPP and the control output node,
- a resistance value of the variable resistance means is controlled by at least one of the groups of the address control signals, and
- the groups of the address control signals from the preceding stage row decoder are signals of a non-boosted power supply potential.
3 more elements
A word line selection circuit comprising:
- a first stage having a variable resistance circuit composed of one transistor controlled by an address decode signal, said address decode signal being configured to have a first voltage swing;
- and
- a second stage coupled to said first stage, and outputting an output signal to a word line, said output signal being configured to have a second voltage swing larger than said first voltage swing.
Dependencies are inferred from the claim text.