Semiconductor memory device, memory controller that controls the same, and information processing system

A memory controller that controls a semiconductor memory device capable of entering in a power-down mode, the memory controller comprising:

• a first output terminal that outputs a power-down command that causes the semiconductor memory device to enter in the power-down mode;
• a second output terminal that outputs a selection signal;
• and
• a control circuit that changes the selection signal to a first state simultaneously with an output of the power-down command when a DLL circuit included in the semiconductor memory device is suspended in the power-down mode, and changes the selection signal to a second state simultaneously with an output of the power-down command when the DLL circuit is operated in the power-down mode.

An information processing system comprising:

• a semiconductor memory device;
• and
• a memory controller that controls the semiconductor memory device, wherein
• the semiconductor memory device comprises:
• a memory cell array that includes a plurality of memory cells;
• an output buffer that outputs read data read from the memory cell array to the memory controller;
• a DLL circuit that controls an operation timing of the output buffer;
• a power-down control circuit that suspends an operation of a predetermined internal circuit in response to issuance of a power-down command from the memory controller;
• and
• an external terminal to which a selection signal is input from the memory controller simultaneously with issuance of the power-down command, and wherein
• the power-down control circuit suspends an operation of the DLL circuit when the selection signal indicates a first state and continues an operation of the DLL circuit when the selection signal indicates a second state.