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US 2010/0302886 A1Published application
Mat compress circuit and semiconductor memory device having the same
AssigneeHynix Semiconductor Inc.
InventorYoung Geun CHOI
Life of this patent
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Abstract
A mat compress circuit includes a pre-control signal generator that generates a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank selection address in a mat compression test, and a control signal transmitter that inverts and transfers the first and second pre-control signals in response to a switching signal activated when there is an input of a block selection address in the mat compression test.
Claims22
A mat compress circuit, comprising:
- a pre-control signal generator configured to generate a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank selection address in a mat compression test;
- and
- a control signal transmitter configured to invert and transfer the first pre-control signal and the second pre-control signal in response to a switching signal activated according to an input of a block selection address in the mat compression test.
A semiconductor memory device, comprising:
- a mat including a first block corresponding to an up bank and a second block corresponding to a down bank, the mat being shared by a first bit-line sense amplifier and a second bit-line sense amplifier;
- a switching signal generator configured to generate a switching signal being activated when the first block is selected in a mat compression test;
- a control signal generator configured to generate first control signal and a second control signal that are alternatively activated in response to an up/down bank selection address during the mat compression test, the first and second control signals being inverted in phase according to the switching signal;
- a first mat controller configured to control a data exchange between the first bit-line sense amplifier and a local input/output line in response to the first control signal and the second control signal;
- and
- a second mat controller configured to control a data exchange between the second bit-line sense amplifier and the local input/output line in response to the second control signal.
3 more elements
Dependencies are inferred from the claim text.