Dual power rail word line driver and dual power rail word line driver array

A word line driver array for a memory array, comprising:

• a first common transistor, having a gate for receiving a first pulse signal, a first terminal coupled to a ground and a second terminal;
• and
• a plurality of dual power rail word line drivers, each driving a word line of the memory array according to a predecode signal from a decoder powered by a first supply voltage, wherein each of the plurality of dual power rail word line drivers comprises:
• a signal buffering unit coupled between the word line and a node;
• a first transistor coupled between the second terminal of the first common transistor and the node, wherein the first transistor is controlled by the predecode signal;
• and
• a second transistor coupled between the node and a second supply voltage higher than or equal to the first supply voltage, having a gate for receiving a second pulse signal;
• wherein the signal buffering unit provides a word line signal corresponding to the predecode signal to the memory array via the word line when the second transistor is turned off and the first common transistor is turned on, and there is no level shifter on a critical timing path of the dual power rail word line driver.