Semiconductor memory device and method of controlling the same

A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals is supplied from an external of the dynamic random access memory chip, comprising:

• a memory core with a plurality of memory cells:
• an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line;
• a command decoder that receives a plurality of control signals and generates an internal command signal;
• and
• a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not performed,
• wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes a reference voltage generator, a detector and a booster circuit.

A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals is supplied from an external of the dynamic random access memory chip, comprising:

• a memory core with a plurality of memory cells;
• an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage the memory core via the internal power supply line;
• a command decoder that receives a plurality of control signals and generates an internal command signal;
• and
• a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not performed,
• wherein the internal voltage generator includes a plurality of booster circuits, coupled to the low power entry circuit, and at least one of the plurality of booster circuits is deactivated in response to the low power signal, and
• wherein the internal voltage generator includes a reference voltage generator and a detector.

A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals is supplied from an external of the dynamic random access memory chip, comprising:

• a memory core including a plurality of memory cells;
• an internal voltage generator, coupled to the memory core via an internal power supply line, that generates an internal voltage based on an external voltage and supplies the internal voltage to the memory core via the internal power supply line;
• a command decoder that receives a plurality of control signals and generates an internal command signal;
• and
• a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not preformed,
• wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes a reference voltage generator, a comparator and a regulator.

A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals is supplied from an external of the dynamic random access memory chip, comprising:

• an internal voltage generator that generates a negative internal voltage based on an external voltage and supplies the negative internal voltage to the substrate via an internal power supply line;
• a command decoder that receives a plurality of control signals and generates an internal command signal;
• and
• a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not performed,
• wherein the internal voltage generator stops supplying the negative internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes an oscillator and a pumping circuit.

A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals is supplied from an external of the dynamic random access memory chip, comprising:

• an internal voltage generator that generates a negative internal voltage based on an external voltage and supplies the negative internal voltage to the substrate via an internal power supply line;
• a command decoder that receives a plurality of control signals and generates an internal command signal;
• a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not performed;
• a detector that detects a level of the internal voltage and outputs a detected signal;
• and
• a plurality of pumping circuits, coupled to the detector, that do pumping operations in response to the detected signal.
• wherein the internal voltage generator stops supplying the negative internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device,
• wherein the internal voltage generator includes an oscillator and a pumping circuit, and
• wherein the external power voltage is supplied to the internal power supply line in the low power consumption mode.

A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals is supplied from an external of the dynamic random access memory chip, comprising:

• a bit line coupled to a memory cell;
• an internal voltage generator that generates an internal voltage based on an external voltage and supplies the internal voltage to precharge the bit line;
• a command decoder that receives a plurality of control signals and generates an internal command signal;
• and
• a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not performed,
• wherein the internal voltage generator, coupled to the low power entry circuit, stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and
• wherein the internal voltage generator includes a reference voltage generator and a comparator.

A dynamic random access memory chip formed on a silicon substrate which performs a read operation or a write operation when a plurality of control signals is supplied from an external of the dynamic random access memory chip, comprising:

• a memory core with a plurality of memory cells;
• an internal voltage generator that generates an internal voltage based on an external voltage and supplies the internal voltage to the memory core via the internal power supply line;
• a command decoder that receives a plurality of control signals and generates an internal command signal;
• and
• a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation on all of the plurality of memory cells is not performed,
• wherein the internal voltage generator, coupled to the low power entry circuit, stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, wherein the internal voltage generator includes a reference voltage generator, a plurality of comparators coupled to the reference voltage generator, and a generator coupled to at least one of the plurality of comparators,
• wherein the reference voltage generator generates a reference voltage, the plurality of comparators compare the internal voltage with the reference voltage and output compared signals, and the generator receives the compared signals and generates the internal voltage.