Memory device having reduced standby current and memory system including same

A memory device comprising:

• a plurality of banks;
• a single first generator configured to generate a standby current in response to a standby signal;
• a plurality of second generators, each configured to provide an active current to a corresponding one of the plurality of banks in response to a corresponding one of a plurality of active signals;
• and
• a plurality of switches, each being commonly connected between the first generator and each one of the plurality of banks and configured to provide the active current to a corresponding one of the plurality of banks in response to a corresponding one of the plurality of active signals.

A memory system comprising:

• a central processing unit (CPU) configured to provide a control signal;
• and
• a memory device configured to operate in response to the control signal,
• wherein the memory device comprises:
• a plurality of banks:
• a single first generator configured to generate a standby current in response to a standby signal;
• and
• a switching circuit configured to provide the standby current to a bank in the plurality of banks in response to a corresponding active signal.