Semiconductor device having nonvolatile memory element and data processing system including the same

A data processing system comprising a semiconductor device and a controller that issues an external reset signal to the semiconductor device,

• wherein the semiconductor device includes:
• a timing control circuit that activates a first internal reset signal in response to transition of the external reset signal and activates a second internal reset signal based on an activation period of the external reset signal;
• a nonvolatile memory element;
• a read-out circuit that reads out a content of the nonvolatile memory element in response to the first internal reset signal;
• and
• a first latch circuit that holds therein the content read out by the read-out circuit and that is reset by the second internal reset signal,
• wherein the controller activates the external reset signal at least when a power is applied to the semiconductor device.

A semiconductor device comprising:

• a timing control circuit producing first and second reset signals, the first reset signal taking an active level during the second reset signal taking an inactive level, and the second reset signal taking an active level during the first reset signal taking an inactive level;
• an information storing element;
• a read-out circuit coupled to the timing control circuit and the information storing element and activated in response to the active level of the first reset signal to read out information stored in the information storing element;
• and
• a latch circuit coupled to the timing control circuit and the read-out circuit and temporarily holding an output of the read-out circuit, the latch circuit being cleared in response to the active level of the second reset signal.