Semiconductor memory device, information processing system including the same, and controller
AssigneeElpida Memory, Inc.
InventorsYasushi Takahashi, Toru Ishikawa
Life of this patent
Estimating the term…
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AssigneeElpida Memory, Inc.
InventorsYasushi Takahashi, Toru Ishikawa
Estimating the term…
To include first and second data input/output terminals allocated to first and second memory circuit units, respectively, and an address terminal allocated in common to these memory circuit units. When a first chip selection signal is activated, the first memory circuit unit performs a read operation or a write operation via the first data input/output terminal based on an address signal regardless of an operation of the second memory circuit unit. When a second chip selection signal is activated, the second memory circuit unit performs a read operation or a write operation via the second data input/output terminal based on the address signal regardless of an operation of the first memory circuit unit. With this configuration, a wasteful data transfer can be prevented, and the effective data transfer rate can be increased.
A semiconductor device comprising:
A system comprising:
A controller comprising:
Dependencies are inferred from the claim text.