Mode-register reading controller and semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorYin Jae LEE
Life of this patent
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Abstract
A mode-register reading controller includes a switching signal generator, first and second transmitters, and a control signal generator. The switching signal generator generates a switching signal that is activated when the reset command is input during a mode-register reading operation. The first transmitter buffers and transfers the mode-register read signal in response to the switching signal. The second transmitter, in response to the switching signal, delays and transfers the enable signal at a predetermined delay time. The control signal generator receives a signal from one of the first and second transmitters and generates a first control signal and a second control signal for transferring the data into a data output buffer from the input/output line.
Claims20
A mode-register reading controller, comprising:
- a switching signal generator configured to generate a switching signal in an activated state when a reset command during a mode-register reading operation is input;
- a first transmitter, in response to the switching signal, is configured to buffer and transfer a mode-register read signal in an activated state after a first delay period from an input of a mode-register read command;
- a second transmitter, in a predetermined delay time in response to the switching signal, is configured to delay and transfer an enable signal in an activated state after a second delay period from an input of the mode-register read command;
- and
- a control signal generator configured to receive a signal from one of the first and second transmitters, to generate a first control signal for loading data into an input/output line from a mode register, and to generate a second control signal for transferring the data into a data output buffer from the input/output line.
A semiconductor memory device, comprising:
- a mode-register reading controller configured to generate a first control signal for loading data into an input/output line in response to an enable signal, during a mode-register reading operation, and configured to generate a second control signal for transferring the data into a data output buffer from the global input/output line, the first and second control signals being generated in response to a mode-register read signal when there is a reset command is input;
- a mode register configured to load the data into the input/output line in response to the first control signal;
- and
- a pipe latch controller configured to generate a pipe-latch control signal to control a pipe latch transferring the data into the data output buffer from the input/output line.
Dependencies are inferred from the claim text.