Buffer control signal generation circuit and semiconductor device

Abstract

A buffer control signal generation circuit includes a burst start signal generator, a command decoder, a burst controller, and a burst column controller. The burst start signal generator shifts a write pulse into a first period to generate a first burst start signal and shifts the write pulse into a second period to generate a second burst start signal, such that the second period being shorter than the first period. The command decoder generates a burst period pulse and a column active pulse in response to the second burst start signal and a column control signal. The burst controller receives the column active pulse and buffers the burst period pulse to generate a burst end signal. The burst column controller generates the column control signal from the burst end signal and the column active pulse.

Dependencies are inferred from the claim text.