Flash memory device operating at multiple speeds
AssigneeSamsung Electronics Co., Ltd.
InventorDae-Seok Byeon
Life of this patent
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Abstract
A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.
Claims8
A method of operating a flash memory device including first and second mats, each one of the first and second mats including a plurality of bit lines connecting a plurality of memory cells, the method comprising:
- precharging the plurality of bit lines in the first mat during a first bit line set-up interval of a set-up interval;
- precharging the plurality of bit lines in the second mat during a second bit line set-up interval of the set-up interval, wherein the first bit line set-up interval and the second bit line set-up interval begin at different times during the set-up interval;
- and
- simultaneously beginning programming of the plurality of memory cells for the first and second mats during a programming execution interval following the set-up interval.
The method of claim 2, wherein the programming of the plurality of memory cells for the first and second mats ends at substantially the same time.
A method of operating a flash memory device in a first operating mode and a second operating mode having different operating speeds, wherein each one of the first and second operating modes comprises a bit line set-up interval and at least one additional interval, wherein the flash memory is divided into first and second mats connected to respective first and second read/write (R/W) circuits and the method comprises:
- during the bit line set-up interval of the second operating mode, controlling operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats, and
- during the at least one additional interval of the second operating mode, controlling the first and second R/W circuits to operate simultaneously.
Dependencies are inferred from the claim text.