Method of testing for a leakage current between bit lines of nonvolatile memory device
AssigneeHynix Semiconductor Inc.
InventorsJae Won CHA, Duck Ju Kim
Life of this patent
Estimating the term…
Abstract
A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.
Claims12
A method of testing for a leakage current between bit lines of a nonvolatile memory device, the method comprising:
- precharging a first bit line of the nonvolatile memory device having a page buffer having the first bit line and a second bit line coupled thereto to a first voltage;
- supplying a second voltage to the second bit line;
- floating the second bit line and evaluating the second bit line for a set period of time;
- and
- detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.
A method of testing for a leakage current between bit lines of a nonvolatile memory device, the method comprising:
- precharging a first bit line to a test voltage;
- supplying a ground voltage to a second bit line neighboring the first bit line after the first bit line has been precharged;
- floating the second bit line and evaluating the second bit line for a set time period after the first bit line has been precharged;
- and
- detecting a shift in a voltage level of the second bit line and testing for the leakage current between the first bit line and the second bit line.
Dependencies are inferred from the claim text.