Data line management in a memory device
AssigneeMicron Technology, Inc.
InventorAndrew Bicksler
Life of this patent
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Abstract
Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.
Claims25
A method for operating a memory device having a plurality of memory cells logically arranged in rows and in columns, the method comprising:
- selecting one or more memory cells of a particular row to be programmed;
- and
- inhibiting two or more adjacent memory cells of the particular row from programming;
- wherein any two memory cells of the particular row that are selected for programming are separated by two or more inhibited adjacent memory cells, regardless of an intended pattern of data values to be programmed into the particular row.
A method for programming a memory device having a plurality of memory cells logically arranged in rows and in columns, the method comprising:
- selecting a particular row of memory cells for programming wherein the particular row of memory cells is arranged into three or more mutually exclusive subsets of memory cells without regard to an intended pattern of data states to be programmed into the particular row of memory cells;
- if it is desired to program a particular subset of memory cells of the particular row, selecting at least one memory cell of the particular subset of memory cells of the particular row for programming while inhibiting each remaining memory cell of the particular subset of memory cells and each remaining subset of memory cells of the particular row from programming and performing a program operation on the particular row of memory cells;
- wherein each memory cell of each subset of memory cells is separated along the particular row of memory cells by a memory cell of each other subset of memory cells.
A method for operating a memory device having a plurality of memory cells logically arranged in rows and in columns each row comprising three or more logical pages of memory cells where each memory cell of each logical page of memory cells of a particular row of memory cells is separated by a memory cell of each of the other logical pages of memory cells of the particular row of memory cells, the method comprising:
- selecting one or more memory cells of a selected logical page of a selected row of memory cells for programming;
- inhibiting remaining memory cells of the selected logical page of the selected row of memory cells from programming;
- inhibiting memory cells of remaining logical pages of memory cells of the selected row of memory cells from programming;
- and
- applying one or more programming pulses to the selected row of memory cells.
A memory device, comprising:
- an array of memory cells logically arranged in rows and in columns where each row of cells is coupled to an access line and each row further comprises three or more logical pages of memory cells where each memory cell of each logical page of memory cells of a particular row of memory cells is separated by a memory cell from each of the other logical pages of memory cells of the particular row;
- a plurality of data lines each coupled to a respective column of memory cells;
- and
- control circuitry, wherein the control circuitry, during a program operation on a first logical page of memory cells of a selected row of memory cells, is configured to bias data lines coupled to one or more memory cells of the first logical page of memory cells in a one-to-one relationship to a first voltage, bias data lines coupled to remaining memory cells of the first logical page of memory cells in a one-to-one relationship to a second voltage, bias data lines coupled to memory cells of each of the other logical pages of memory cells of the selected row of memory cells in a one-to-one relationship to the second voltage and apply a third voltage to an access line coupled to the selected row of memory cells;
- wherein the first voltage is a potential to enable programming of memory cells coupled to the access line and to a data line receiving the first voltage;
- and
- wherein the second voltage is a potential to inhibit programming of memory cells coupled to the access line and to a data line receiving the second voltage.
A memory device, comprising:
- an array of memory cells logically arranged in rows and in columns where each column of cells is coupled to a data line and each row of cells is coupled to an access line;
- and
- control circuitry, wherein the control circuitry, during a program operation on a particular row of memory cells, is configured to selectively bias one of three or more subsets of data lines with a first potential to enable programming of memory cells coupled to data lines biased to the first potential and bias the remaining subsets of data lines with a second potential to inhibit programming of memory cells coupled to those remaining subsets of data lines to selectively program one or more memory cells of the one of the three or more subsets of memory cells of the particular row of memory cells where each subset of data lines is coupled to a corresponding memory cell of each subset of memory cells and where each memory cell of each subset of the particular row of memory cells is separated by a memory cell from each other subset of memory cells.
Dependencies are inferred from the claim text.