Nonvolatile memory device and method of verifying the same

A nonvolatile memory device, comprising:

• a memory cell array configured to include a number of memory cells coupled to a bit line;
• a control circuit configured to output a code signal in response to a verification operation command signal during a verification operation being performed;
• a page buffer operation voltage generator configured to generate a precharge signal and a sense signal in response to the code signal, the sense signals having sequentially lowered voltage levels being outputted in response to a number of verification operations being consecutively repeated;
• and
• a page buffer configured to precharge the bit line in response to the precharge signal and to sense data programmed into the memory cell in response to the sense signal.

A verification method of a nonvolatile memory device having a memory cell array, and including a number of memory cells coupled to a bit line, and a page buffer, having a bit line sense unit configured to couple the bit line to a sense node, the method comprising:

• performing a program operation on a selected one of the memory cells by supplying the selected memory cell with a program voltage;
• precharging the bit line;
• sensing a voltage level of the bit line through the sense node and performing a first verification operation according to the sensed voltage level, the voltage level of the bit line varying according to a program state of the selected memory cell, and the voltage level of the bit line being transmitted to the sense node in response to a first sense signal;
• setting a second sense signal having a voltage level less than that of the first sense signal;
• and
• performing a second verification operation with the second sense signal.

A verification method of a nonvolatile memory device having a memory cell array, and including a number of memory cells coupled to a bit line, and a page buffer, having a bit line sense unit configured to couple the bit line to a sense node, the method comprising:

• performing a program operation on a selected one of the memory cells by supplying the selected memory cell with a program voltage;
• precharging the bit line;
• sensing a voltage level of the bit line through the sense node and performing a verification operation based on the sensed voltage level of the bit line, the voltage level of the bit line varying according to a program state of the selected memory cell, and the voltage level of the bit line being transmitted to the sense node in response to a sense signal supplied to the page buffer;
• resetting a voltage level of the sense signal to be less than that of the previously used sense signal;
• and
• performing again the verification operation and the reset of the sense signal, the verification operation being repeatedly performed N times, N being a positive integer.