Transistor having peripheral channel
AssigneeMicron Technology, Inc.
InventorVladimir Mikhalev
Life of this patent
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Abstract
Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain region formed to extend below the channel region such that the channel region is formed around a perimeter of the source/drain region. Such transistors should facilitate a reduction in edge effect and leakage as the channel of the transistor is not bordering on an isolation region. Additionally, the use of a source/drain region extending through a channel region facilitates high-power, high-voltage operation.
Claims23
A transistor, comprising:
- a control gate;
- a gate dielectric formed between the control gate and a semiconductor material;
- a channel region formed in the semiconductor material below the gate dielectric;
- a first source/drain region formed in the semiconductor material around a perimeter of the channel region;
- a second source/drain region extending below the gate dielectric and through the channel region, such that the channel region is formed around a perimeter of the second source/drain region.
A memory device, comprising:
- an array of memory cells logically arranged in rows and columns, with access lines coupled to control gates of the memory cells;
- control logic for controlling access to the array of memory cells;
- and
- a row decode circuitry for selectively driving access lines, wherein the row decode circuitry comprises at least one transistor having a first source/drain region coupled to an access line, a control gate coupled to receive a control signal, and a second source/drain region coupled to receive a potential to be applied to the access line, the transistor comprising:
- a gate dielectric formed between the control gate and a semiconductor substrate;
- and
- a channel region formed in the semiconductor material below the gate dielectric;
- wherein the first source/drain region is formed in the semiconductor material around a perimeter of the channel region;
- and
- wherein the second source/drain region extends below the gate dielectric and through the channel region, such that the channel region is formed around a perimeter of the second source/drain region.
A memory device, comprising:
- an array of memory cells logically arranged in rows and columns, with access lines coupled to control gates of the memory cells;
- control logic for controlling access to the array of memory cells;
- and
- a row decode circuitry for selectively driving access lines, wherein the row decode circuitry comprises at least one transistor having a first source/drain region coupled to an access line, a control gate coupled to receive a control signal, and a second source/drain region coupled to receive a potential to be applied to the access line, the transistor comprising:
- a gate dielectric formed between the control gate and a semiconductor substrate;
- a channel region formed in the semiconductor material below the gate dielectric;
- a well region formed at a level below the channel region and coupled to a bottom portion of the second source/drain region and having a same conductivity type as a conductivity type of the second source/drain region;
- and
- one or more contacts coupled to the first source/drain region;
- wherein the one or more contacts are further coupled to an access line;
- wherein the first source/drain region is formed in the semiconductor material around a perimeter of the channel region;
- and
- wherein the second source/drain region extends below the gate dielectric and through the channel region, such that the channel region is formed around a perimeter of the second source/drain region.
Dependencies are inferred from the claim text.