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US 2010/0302847 A1Published application
Multi-level nand flash memory
OwnerHiromitsu Komai, Teruo Takagiwainventors
Life of this patent
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Abstract
According to one embodiment, a multi-level NAND flash memory executes a writing of an upper data to a LM flag. When an address of a flag assigns a bad column, a data transfer control circuit and a address control circuit control a write operation of upper data in the flag by an operation of transmitting the upper data of the flag from the bad column data hold circuit to the data latch circuit, reading the lower data of the flag from a redundancy column storing the flag into the data latch circuit, generating an address of a redundancy column storing the flag based on the address of the flag, and forcefully inverting the lower data of the flag in the data latch circuit by using the address of the redundancy column storing the flag.
Claims15
A multi-level NAND flash memory comprising:
- a memory cell array;
- a data transfer control circuit arranged on one side of the memory cell array, and configured to control data transfer to the memory cell array;
- a data latch circuit arranged between the memory cell array and the data transfer control circuit;
- a bad column data hold circuit configured to temporarily hold data of a bad column in read/write operation;
- a data buffer serving as an interface for data;
- an address buffer serving as an interface for an address;
- a switch circuit configured to transfer data between two of the data buffer, the data latch circuit, and the bad column data hold circuit;
- and
- an address control circuit configured to transfer the address to the bad column data hold circuit, and to prohibit, if the address is determined to assign a bad column in the bad column data hold circuit, transfer operation of the address to the data transfer control circuit,
- wherein a threshold distribution of a memory cell constituting the memory cell array is set to a first state or a second state in an ascending order of a threshold in a state in which lower data is written, and is set to a third state, a fourth state, a fifth state, or a sixth state in an ascending order of a threshold in a state in which lower data and upper data are written, and
- the second state is different from the fourth state, the fifth state, and the sixth state,
- wherein the memory cell array includes a main area storing main data, a flag area storing a flag for determining whether the main data contains only lower data or both lower data and upper data, and a redundancy area having a redundancy column,
- wherein a threshold distribution of the flag is set to the first state in a state in which lower data is written, and is set to the fifth state in a state in which lower data and upper data are written, and
- wherein when an address of the flag assigns a bad column, the data transfer control circuit and the address control circuit control a write operation of upper data in the flag by an operation of
- transmitting the upper data of the flag from the bad column data hold circuit to the data latch circuit,
- reading the lower data of the flag from a redundancy column storing the flag into the data latch circuit,
- generating an address of a redundancy column storing the flag based on the address of the flag, and
- forcefully inverting the lower data of the flag in the data latch circuit by using the address of the redundancy column storing the flag.
15 more elements
A method of writing data to a multi-level NAND flash memory comprising:
- a memory cell array;
- a data transfer control circuit arranged on one side of the memory cell array, and configured to control data transfer to the memory cell array;
- a data latch circuit arranged between the memory cell array and the data transfer control circuit;
- a bad column data hold circuit configured to temporarily hold data of a bad column in read/write operation;
- a data buffer serving as an interface for data;
- an address buffer serving as an interface for an address;
- a switch circuit configured to transfer data between two of the data buffer, the data latch circuit, and the bad column data hold circuit;
- and
- an address control circuit configured to transfer the address to the bad column data hold circuit, and to prohibit, if the address is determined to assign a bad column in the bad column data hold circuit, transfer operation of the address to the data transfer control circuit,
- wherein a threshold distribution of a memory cell constituting the memory cell array is set to a first state or a second state in an ascending order of a threshold in a state in which lower data is written, and is set to a third state, a fourth state, a fifth state, or a sixth state in an ascending order of a threshold in a state in which lower data and upper data are written, and
- the second state is different from the fourth state, the fifth state, and the sixth state,
- wherein the memory cell array includes a main area storing main data, a flag area storing a flag for determining whether the main data contains only lower data or both lower data and upper data, and a redundancy area having a redundancy column,
- wherein a threshold distribution of the flag is set to the first state in a state in which lower data is written, and is set to the fifth state in a state in which lower data and upper data are written, and
- wherein when an address of the flag assigns a bad column, upper data is written in the flag after an operation of
- transmitting the upper data of the flag from the bad column data hold circuit to the data latch circuit,
- reading the lower data of the flag from a redundancy column storing the flag into the data latch circuit,
- generating an address of a redundancy column storing the flag based on the address of the flag, and
- forcefully inverting the lower data of the flag in the data latch circuit by using the address of the redundancy column storing the flag.
15 more elements
A multi-level NAND flash memory comprising:
- a memory cell array;
- a data transfer control circuit arranged on one side of the memory cell array, and configured to control data transfer to the memory cell array;
- a data latch circuit arranged between the memory cell array and the data transfer control circuit;
- a bad column data hold circuit configured to temporarily hold data of a bad column in read/write operation;
- a data buffer serving as an interface for data;
- an address buffer serving as an interface for an address;
- a switch circuit configured to transfer data between two of the data buffer, the data latch circuit, and the bad column data hold circuit;
- and
- an address control circuit configured to transfer the address to the bad column data hold circuit, and to prohibit, if the address is determined to assign a bad column in the bad column data hold circuit, transfer operation of the address to the data transfer control circuit,
- wherein the memory cell array includes a main area storing main data, a flag area storing a flag for determining whether the main data contains only lower data or both lower data and upper data, and a redundancy area having a redundancy column, and
- wherein when an address of the flag assigns a bad column, the data transfer control circuit and the address control circuit control a write operation of upper data in the flag by an operation of
- transmitting the upper data of the flag from the bad column data hold circuit to the data latch circuit,
- reading the lower data of the flag from a redundancy column storing the flag into the data latch circuit,
- generating an address of a redundancy column storing the flag based on the address of the flag, and
- forcefully inverting the lower data of the flag in the data latch circuit by using the address of the redundancy column storing the flag.
12 more elements
Dependencies are inferred from the claim text.