Memory device and methods for fabricating and operating the same

A method for fabricating a memory device, comprising:

• providing a substrate;
• forming a plurality of trenches in the substrate;
• forming a plurality of first doped regions in the substrate adjacent to both sides of an upper portion of each trench respectively, wherein the first doped regions between the neighbouring trenches are separated from each other;
• forming a plurality of second doped regions in the substrate under bottoms of the trenches respectively;
• forming a charge storage layer conformally on the substrate and on a surface of the trenches;
• and
• forming a conductive layer on the charge storage layer, wherein the conductive layer fills the trenches,
• wherein six physical bits are formed in the charge storage layer in a single memory cell at junctions of the first doped regions and the second doped regions respectively.

A method for operating a memory device, comprising:

• providing a memory cell, comprising:
• a substrate having two trenches formed therein;
• a conductive layer, disposed on the substrate and filling the trenches;
• a charge storage layer, disposed between the substrate and the conductive layer;
• two first doped regions, configured in the substrate adjacent to an upper portion of each trench respectively, wherein the first doped regions between the neighbouring trenches are separated from each other;
• and
• two second doped regions, configured in the substrate under bottoms of the trenches respectively, wherein the second doped regions and the first doped regions are separated from each other, such that six bits are formed in the charge storage layer at junctions of the first doped regions and the second doped regions respectively;
• when performing a programming operation, applying a first voltage to the conductive layer, applying a second voltage to a selected doped region adjacent to a selected bit, applying a third voltage to one of non-selected doped regions neighboring with the selected bit along the conductive layer, applying a fourth voltage to the substrate, and floating the other two non-selected doped regions,
• wherein the first voltage is higher than the fourth voltage, and the second voltage is higher than the third voltage to program the selected bit.