# US 2010/0302844 A1 · Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling

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- Number: US 2010/0302844 A1
- Document ID: US20100302844A1
- Status: Published application
- Kind: A1
- Application number: 12/818,565
- Filed: 2010-06-18
- Published: 2010-12-02
- Earliest claimed: 2006-05-22
- Assignees: Micron Technology, Inc.
- Inventors: Hagop A. Nazarian; Aaron Yip
- Web page: https://patentgrep.com/patent/US20100302844A1

## CPC

- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- H10B 41/10: characterised by the top-view layout
- H10B 41/30: characterised by the memory core region
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10D 89/10: Integrated device layouts
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling.

## Claims

### Claim at position 1

1-21. (canceled)

### Claim 22

A non-volatile memory device comprising:
an array of non-volatile memory cells, each memory cell comprising a charge storage structure;
a plurality of bit lines each connected to a plurality of memory cells in a string,
a plurality of word lines each connected to a plurality of memory cells, wherein side walls of the charge storage structure of a first memory cell in a string are not vertically aligned with side wall the charge storage structure of an adjacent memory cell in the string.

### Claim 23 (depends on 22)

The non-volatile memory device of claim 22, wherein the non-volatile memory device is a flash memory device.

### Claim 24 (depends on 22)

The non-volatile memory device of claim 22, wherein the charge storage structure comprises a floating gate.

### Claim 25 (depends on 22)

The non-volatile memory device of claim 22, wherein the plurality of bit lines and corresponding memory cells are arranged so that the plurality of bit lines diagonally intersect with the plurality of word lines at corresponding memory cells.

### Claim 26 (depends on 26)

The non-volatile memory device of claim 26, wherein the plurality of bit lines are nonlinear.

### Claim 27

A non-volatile memory device comprising:
an array of non-volatile memory cells, each memory cell comprising a charge storage structure;
a plurality of bit lines each connected to a plurality of memory cells in a string,
a plurality of word lines each connected to a plurality of memory cells, wherein side walls of each charge storage structure connected to a first word line are not horizontally aligned with side walls of each charge storage structure of each memory cell connected to a second word line, the first and second word lines being adjacent one another.

### Claim 28 (depends on 27)

The non-volatile memory device of claim 27, wherein the plurality of bit lines are nonlinear.

### Claim 29 (depends on 27)

The non-volatile memory device of claim 27, wherein the charge storage structure comprises a floating gate.

### Claim 30 (depends on 27)

The non-volatile memory device of claim 27, wherein the plurality of bit lines and corresponding memory cells are arranged so that the plurality of bit lines diagonally intersect with the plurality of word lines at corresponding memory cells.