Phase change random access memory apparatus for controlling data transmission
AssigneeHynix Semiconductor Inc.
InventorTae Hun YOON
Life of this patent
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Abstract
A phase change memory apparatus includes: a plurality of sub blocks; a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks; and a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal, which is effective in improving areal efficiency by sharing the latch block among the sub blocks in the unit mat.
Claims21
A phase change memory apparatus, comprising:
- a plurality of sub blocks;
- a latch block connected in common with the sub blocks through a read bus, and configured to latch data from one of the sub blocks;
- and
- a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with the data of the write bus to generate a comparison signal.
A phase change memory apparatus, comprising:
- a mat including a plurality of sub blocks;
- and
- a latch block disposed in the mat and connected in common with the sub blocks through a read bus, configured to latch data of one of the sub blocks that is selected by a sub-block selection signal.
A phase change memory apparatus, comprising:
- a plurality of sub blocks;
- a latch block connected in common with the sub blocks through a read bus and configured to latch data from one of the sub blocks;
- and
- a comparator connected in common with the sub blocks to receive data from a write bus, and configured to compare data of the latch block with data of the write bus,
- wherein, when one of the sub blocks is selected in response to a write command, data that is read out from the selected sub block is compared to the data from the write bus.
A phase change memory apparatus, comprising:
- a plurality of sub blocks;
- a latch block connected in common with at least two sub blocks through a read bus, and configured to latch data from one of the at least two sub blocks;
- and
- a comparator connected in common with the at least two sub blocks to receive data from a write bus, and configured to compare data in the latch block with the data of from write bus to generate a comparison signal.
Dependencies are inferred from the claim text.