Statis source plane in stram

A memory array, comprising:

• a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array, each magnetic tunnel junction cell electrically coupled to a transistor, each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell;
• a plurality of bit lines arranged in columns, each bit line column electrically coupled at least selected magnetic tunnel junction cells along the column;
• a plurality of word lines arranged in rows being orthogonal to the word line rows, each word line row electrically couples at least selected transistors along the row;
• and
• a single source line electrically connecting all the transistors in the array.

A memory array, comprising:

• a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array, each magnetic tunnel junction cell electrically coupled to a transistor, each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell;
• a plurality of bit lines arranged in columns, each bit line column electrically coupled at least selected magnetic tunnel junction cells along the column;
• a plurality of word lines arranged in rows being orthogonal to the word line rows, each word line row electrically couples at least selected transistors along the row;
• and
• a single static source line electrically connecting all the transistors in the 2 by 2 array, the single static source line configured to provide a constant voltage to all the transistors in the array when writing either the high resistance state or low resistance state.