US 2010/0302838 A1 · Read disturb-free SMT reference cell scheme

Abstract

We describe a reference cell structure for determining data storing cell resistances in an SMT (spin moment transfer) MTJ (magnetic tunneling junction) MRAM array by comparing data cell currents with those of the reference cell. Since the reference cell also utilizes spin moment transfer (SMT) magnetic tunneling junction (MTJ) cells, there would ordinarily be the danger that the act of reading the reference cell could change its magnetization orientations and be a source of error for subsequent comparisons. Therefore the present invention describes a new circuit arrangement for the reference cell that directs read currents through two SMT MTJ cells in opposite directions so that the transfer of spin moments cannot affect the relative magnetization directions of the cells.

Claims20

Dependent claims

A reference cell for an MRAM array, comprising:

a first SMT MTJ cell including a fixed layer and a free layer set in a maximum resistance magnetization configuration;
a second SMT MTJ cell including a fixed layer and a free layer set in a minimum resistance magnetization configuration;
a word line for accessing each of said first and second cells through an accessing transistor;
a bit line for sending a reference current through each of said first and second cells when said word line is accessed and said transistors are on;
wherein
a first portion of said reference current flows through said first cell in a direction from a fixed to a free layer and a remaining portion of said reference current flows in said second cell in a direction from a free layer to a fixed layer, whereby
said magnetization configurations are resistant to change caused by said reference current.

4 more elements

A method of fabricating a reference cell for an MRAM array comprising:

providing a substrate;
forming on said substrate two substantially identical read transistors, wherein gate electrodes of said read transistors are connected to a common word line and wherein drain connections of said transistors are connected to ground;
forming a separate bottom electrode layer on said substrate for each of two SMT MTJ cells;
forming a separate bottom electrode metal piece adjacent to one of said electrode layers;
forming a first SMT MTJ cell on one of said bottom electrode layers and a second SMT MTJ cell on the other of said bottom electrode layers, wherein the first SMT MTJ cell is proximal to said bottom electrode metal piece;
forming a blanket dielectric layer surrounding said first and second MTJ cells, said bottom electrode metal piece, said two read transistors and said common word line;
planarizing said dielectric layer, thereby substantially exposing upper surfaces of said two SMT MTJ cells;
forming through said planarized dielectric layer a first and second conducting via, wherein said first conducting via electrically contacts the bottom electrode of said first SMT MTJ cell and said second conducting via electrically contacts said bottom electrode metal piece;
forming a bit line layer and an adjacent bit line metal piece on said planarized dielectric layer, said bit line layer electrically contacting said first via and electrically contacting an upper surface of said second SMT MTJ cell and said bit line metal piece electrically contacting said second via and an upper surface of said first SMT MTJ cell;
connecting a source of one of said two transistors to a lower electrode of said second SMT MTJ cell;
connecting a source of the second of said two transistors to said bottom electrode metal piece.

8 more elements

Dependencies are inferred from the claim text.

Read disturb-free SMT reference cell scheme

Life of this patent

Read disturb-free SMT reference cell scheme

Life of this patent

Abstract

Claims20