Semiconductor device having nonvolatile memory element and manufacturing method thereof
AssigneeElpida Memory, Inc.
InventorsKazuhiro Teramoto, Hiroki Fujisawa, Susumu Takahashi
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Abstract
To provide a semiconductor device including a pair of antifuse elements at either a high level or a low level, an OR circuit that outputs different logic information for a case that at least one of the antifuse elements is at a high level and a case that both of the antifuse elements are at a low level, and an exclusive OR circuit that outputs different logic information for a case that the logic states are different from each other and a case that they are same as each other.
Claims17
A semiconductor device comprising:
- a pair of nonvolatile memory elements respectively being in either a first logic state or a second logic state;
- a first logic circuit that outputs different logic information for cases between at least one of the pair of nonvolatile memory elements being in the first logic state and both of the pair of nonvolatile memory elements being in the second logic state;
- and
- a second logic circuit that outputs different logic information for cases between the logic states of the pair of nonvolatile memory elements being different from each other and the logic states of the pair of nonvolatile memory elements being same as each other.
A semiconductor device comprising a plurality of antifuse units, each of the antifuse units comprising:
- a plurality of antifuse elements;
- a first circuit that determines whether at least one of the antifuse elements are in a conductive state;
- and
- a second circuit that determines whether all of the antifuse elements are in the conductive state or in an insulating state.
A semiconductor device comprising:
- first and second fuse elements each representing one of first and second states;
- and
- a first logic circuit coupled to the first and second fuse elements to produce a first logic level when the first fuse element is the same in state as the second fuse element and a second logic level when the first fuse element is different in state from the second fuse element.
Dependencies are inferred from the claim text.