Back to results
US 2010/0302831 A1Published application
Semiconductor storage device
AssigneeKabushiki Kaisha Toshiba
InventorsYasuhisa Takeyama, Osamu Hirabayashi, Takahiko Sasaki, Yuki Fujimura
Life of this patent
Estimating the term…
Abstract
A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.
Claims20
A semiconductor storage device comprising a memory cell, wherein the memory cell comprises:
- a first drive transistor;
- a second drive transistor;
- a first load transistor connected to the first drive transistor in series;
- a second load transistor connected to the second drive transistor in series;
- a first write-only transfer transistor whose drain is connected to a gate of the second drive transistor, a gate of the second load transistor, a drain of the first drive transistor, and a drain of the first load transistor;
- a second write-only transfer transistor whose drain is connected to a drain of the second drive transistor, a drain of the second load transistor, a gate of the first drive transistor, and a gate of the first load transistor;
- a first read-only drive transistor whose gate is connected to the gate of the first drive transistor, the gate of the first load transistor, the drain of the second drive transistor, and the drain of the second load transistor;
- a first read-only transfer transistor whose drain is connected to a drain of the first read-only drive transistor;
- a first column selection transistor whose drain is connected to a source of the first write-only transfer transistor;
- a second column selection transistor whose drain is connected to a source of the second write-only transfer transistor;
- a word line connected to a gate of the first write-only transfer transistor, a gate of the second write-only transfer transistor, and a gate of the first read-only transfer transistor;
- a first write bit line connected to a source of the first column selection transistor;
- a second write bit line connected to a source of the second column selection transistor;
- a first read bit line connected to a source of the first read-only transfer transistor;
- and
- a column selection line connected to a gate of the first column selection transistor and a gate of the second column selection transistor.
13 more elements
A semiconductor storage device comprising a memory cell, wherein the memory cell comprises:
- a first drive transistor;
- a second drive transistor;
- a first load transistor connected to the first drive transistor in series;
- a second load transistor connected to the second drive transistor in series;
- a first write-only transfer transistor whose drain is connected to a gate of the second drive transistor, a gate of the second load transistor, a drain of the first drive transistor, and a drain of the first load transistor;
- a second write-only transfer transistor whose drain is connected to a drain of the second drive transistor, a drain of the second load transistor, a gate of the first drive transistor, and a gate of the first load transistor;
- a first read-only drive transistor in which a front gate and a back gate are formed, whose front gate is connected to the gate of the first drive transistor, the gate of the first load transistor, the drain of the second drive transistor, and the drain of the second load transistor;
- a first read-only transfer transistor whose drain is connected to a drain of the first read-only drive transistor;
- a first column selection transistor whose drain is connected to a source of the first write-only transfer transistor;
- a second column selection transistor whose drain is connected to a source of the second write-only transfer transistor;
- a write word line connected to a gate of the first write-only transfer transistor and a gate of the second write-only transfer transistor;
- a read word line connected to a gate of the first read-only transfer transistor;
- a first write bit line connected to a source of the first column selection transistor;
- a second write bit line connected to a source of the second column selection transistor;
- a first read bit line connected to a source of the first read-only transfer transistor;
- and
- a column selection line connected to a gate of the first column selection transistor, a gate of the second column selection transistor, and a back gate of the first read-only drive transistor.
14 more elements
Dependencies are inferred from the claim text.