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US 2010/0302830 A1Published application
Semiconductor memory device
OwnerJong Hyun WANGinventor
Life of this patent
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Abstract
A semiconductor memory device having a number of chips, each of the chips including a chip enable detection unit configured to simultaneously output a first signal and a second signal in response to a chip enable signal, a chip operation detection unit configured to output an operation state signal in response to the first signal, and an internal circuit configured to operate in response to a power source voltage and a control signal in response to the second signal being received.
Claims20
A semiconductor memory device having a number of chips, each of the chips comprising:
- a chip enable detection unit configured to simultaneously output a first signal and a second signal in response to a chip enable signal;
- a chip operation detection unit configured to output an operation state signal in response to the first signal;
- and
- an internal circuit configured to operate in response to a power source voltage and a control signal in response to the second signal being received.
1 more element
A semiconductor memory device, comprising:
- a number of memory chips;
- chip enable detection units included in the respective memory chips and each configured to simultaneously output a first signal and a second signal in response to a chip enable signal;
- chip operation detection units included in the respective memory chips and each configured to output an operation state signal in response to the first signal;
- and
- internal circuits included in the respective memory chips and each configured to operate in response to the second signal and to output input/output (I/O) signals,
- wherein wires coupled to the respective memory chips and configured to transfer the respective operation state signals are bundled into groups.
3 more elements
A semiconductor memory device, comprising:
- a number of memory chips included in one package and coupled to respective pins of the package through respective wires;
- chip enable detection units included in the respective memory chips and each configured to simultaneously output a first signal and a second signal in response to a chip enable signal;
- chip operation detection units included in the respective memory chips and each configured to output an operation state signal in response to the first signal;
- and
- an internal circuit included in the respective memory chips, each internal circuit configured to operate in response to the second signal,
- wherein the respective memory chips output operation state signals, the operation state signals being grouped together.
3 more elements
Dependencies are inferred from the claim text.