Addressing circuit of semiconductor memory device and addressing method therefor
AssigneeHynix Semiconductor Inc.
InventorJin Su Park
Life of this patent
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Abstract
The addressing circuit of a semiconductor memory device includes a plurality of register units coupled to an input unit and a plurality of memory cell arrays, wherein the plurality of register units are configured to store inputted data in response to register control signals, and a control unit configured to generate the register control signals, using defect information of respective memory cell arrays, to control whether or not the register units store the inputted.
Claims13
An addressing circuit of a semiconductor memory device, the addressing circuit comprising:
- a plurality of register units coupled to an input unit and a plurality of memory cell arrays, wherein the plurality of register units are configured to store inputted external data in response to register control signals;
- and
- a control unit configured to generate the register control signals, using defect information of respective memory cell arrays, to control whether or not the register units store the inputted external data.
An addressing method of a semiconductor memory device which comprises a plurality of memory cell arrays, the addressing method comprising:
- receiving external data;
- determining whether a memory cell array of the plurality of memory cell arrays is a normal memory cell array or a defective memory cell array depending on defect information;
- and
- assigning the external data inputted sequentially to normal memory cell arrays.
Dependencies are inferred from the claim text.