Code address memory (cam) cell read control circuit of semiconductor memory device and method of reading data of cam cell
AssigneeHynix Semiconductor Inc.
InventorsKyoung Nam KIM, Beom Ju Shin
Life of this patent
Estimating the term…
Abstract
A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device includes a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data, an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals, and a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals. The internal ready/busy signal is generated after the externally input reset signal has reset the CAM cell read circuit.
Claims13
A Code Address Memory (CAM) cell read control circuit of a semiconductor memory device, the circuit comprising:
- a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data;
- an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals;
- and
- a signal generation unit configured to generate an internal ready/busy signal in response to the internal command signals,
- wherein the internal ready/busy signal resets the CAM cell read circuit, the internal ready/busy signal being generated after the externally input reset signal.
A CAM cell read control circuit of a semiconductor memory device, the circuit comprising:
- a CAM cell read circuit configured to read data stored in a CAM cell and to output the read data;
- an internal delay circuit configured to delay an externally input reset signal and to generate a number of internal command signals;
- and
- a signal generation unit configured to generate an internal ready/busy signal to reset the CAM cell read circuit in response to the internal command signals.
A method of reading data stored in a CAM cell of a semiconductor memory device, the method comprising:
- determining whether an externally input reset signal is a first externally input reset signal;
- delaying the externally input reset signal and generating an internal command signal if the externally input reset signal is determined to be a first externally input reset signal;
- generating the internal command signal again to increase a number of times that the internal command signal has been generated upon the number of times that the internal command signal has been generated being less than a set number of times;
- generating an internal ready/busy signal to reset a CAM cell read circuit upon the number of times that the internal command signal has been generated being equal to the set number of times;
- and
- reading data stored in a CAM cell using the CAM cell read circuit.
Dependencies are inferred from the claim text.