Liquid crystal display device, active matrix substrate, liquid crystal panel, liquid crystal display unit, and television receiver

A liquid crystal display device, comprising:

• scanning signal lines;
• first data signal lines and second data signal lines;
• pixels;
• and
• a plurality of storage capacitor wires whose potential is controllable,
• in a case where a direction in which the scanning signal lines extend is referred to as a row direction, the pixels being arrayed in matrix along the row direction and a column direction,
• each pixel array in the column direction being provided correspondingly with one of the first data signal lines and one of the second data signal lines,
• each of the pixels including three subpixels which are connected to identical one of the scanning signal lines, the pixel being associated correspondingly with two storage capacitor wires of the plurality of storage capacitor wires,
• two subpixels of the three subpixels defining respective capacitances with one of the two storage capacitor wires,
• one of the two subpixels being connected to the one of the first data signal lines, and an other one of the two subpixels being connected to the one of the second data signal lines,
• an other subpixel of the three subpixels defining a capacitance with an other one of the two storage capacitor wires, and
• the other subpixel being connected to the one of the first data signal lines or the one of the second data signal lines.

An active matrix substrate, comprising:

• scanning signal lines;
• first data signal lines and second data signal lines;
• pixel regions;
• and
• a plurality of storage capacitor wires,
• in a case where a direction in which the scanning signal lines extend is referred to as a row direction, the pixel regions being arrayed in matrix along the row direction and a column direction,
• each pixel region array in the column direction being provided correspondingly with one of the first data signal lines and one of the second data signal lines,
• each of the pixel regions including four pixel electrodes which are connected to identical one of the scanning signal lines via respective transistors, the pixel region being associated correspondingly with two storage capacitor wires of the plurality of storage capacitor wires,
• two pixel electrodes of the four pixel electrodes defining respective capacitances with one of the two storage capacitor wires,
• one of the two pixel electrodes being connected to the one of the first data signal lines via corresponding one of the transistors, and an other one of the two pixel electrodes being connected to the one of the second data signal lines via corresponding one of the transistors,
• other two pixel electrodes of the four pixel electrodes defining respective capacitances with an other one of the two storage capacitor wires, and
• one of the other two pixel electrodes being connected to the one of the first data signal lines via corresponding one of the transistors, and an other one of the other two pixel electrodes being connected to the one of the second data signal lines via corresponding one of the transistors.

An active matrix substrate, comprising:

• scanning signal lines;
• first data signal lines and second data signal lines;
• pixel regions;
• and
• a plurality of storage capacitor wires,
• in a case where a direction in which scanning signal lines extend is referred to as a row direction, the pixel regions being arrayed in matrix along the row direction and a column direction,
• each pixel region array in the column direction being provided correspondingly with one of the first data signal lines and one of the second data signal lines,
• each of the pixel regions including three pixel electrodes which are connected to identical one of the scanning signal lines via respective transistors, the pixel region being associated correspondingly with two storage capacitor wires of the plurality of storage capacitor wires,
• two pixel electrodes of the three pixel electrodes defining respective capacitances with one of the two storage capacitor wires,
• one of the two pixel electrodes being connected to the one of the first data signal lines via corresponding one of the transistors, and an other one of the two pixel electrodes being connected to the one of the second data signal lines via corresponding one of the transistors,
• an other pixel electrode of the three pixel electrodes defining a capacitance with an other one of the two storage capacitor wires, and
• the other pixel electrode being connected to the one of the first data signal lines or the one of the second data signal lines via corresponding one of the transistors.