Negative capacitance synthesis for use with differential circuits

A circuit, comprising:

• a plurality of cascaded differential stages;
• a first negative capacitance circuit connected between differential nodes of a first one of the plurality of cascaded differential stages;
• and
• a second negative capacitance circuit connected between differential nodes of a second one of the plurality of cascaded differential stages.

A negative capacitance circuit, comprising:

• a first transistor (Q1) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the first transistor (Q1) connected to a first voltage rail;
• a second transistor (Q2) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the first current path terminal (collector or drain) of the second transistor (Q2) connected to the first voltage rail;
• a third transistor (Q3) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the control terminal (base or gate) of the third transistor (Q3) connected to the second current path terminal (emitter or source) of the first transistor (Q1), and the first current path terminal (collector or drain) of the third transistor (Q3) connected to the control terminal (base or gate) of the second transistor (Q2);
• a fourth transistor (Q4) having a control terminal (base or gate) and a current path including a first current path terminal (collector or drain) and a second current path terminal (emitter or source), the control terminal (base or gate) of the fourth transistor (Q4) connected to the second current path terminal (emitter or source) of the second transistor (Q2), and the first current path terminal (collector or drain) of the fourth transistor (Q4) connected to the control terminal (base or gate) of the first transistor (Q1);
• a first bias current source (Ibias) connected between the second current path terminal (emitter or source) of the first transistor (Q1) and a second voltage rail;
• a second bias current source (Ibias) connected between the second current path terminal (emitter or source) of the second transistor (Q1) and the second voltage rail;
• a third bias current source (Ibias) connected between the second current path terminal (emitter or source) of the third transistor (Q3) and the second voltage rail;
• a fourth bias current source (Ibias) connected between the second current path terminal (emitter or source) of the fourth transistor (Q4) and the second voltage rail;
• a first capacitor (C1) connected between the second current path terminal (emitter or source) of the fourth transistor (Q4) and the second voltage rail;
• and
• a second capacitor (C2) connected between the second current path terminal (emitter or source) of the third transistor (Q3) and the second voltage rail.