High frequency receiver preamplifier

6) A folded cascode receiver preamplifier with a CMOS rail-to-rail input, comprising:

• an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, where at a low common mode input voltage only PMOS transistors are active and at a high common mode input voltage only NMOS transistors are active, and where at a middle input common mode voltage, between said low and said high input voltage both PMOS and NMOS transistors are active, said open-loop high frequency differential amplifier further comprising:
• a level shifting stage comprising a transistor pair, said level shifting stage coupled to said differential inputs, said level shifting stage shifting the level of said differential inputs;
• at least a PMOS differential input pair of transistors, where the gates of said PMOS differential input pair are coupled to the outputs of said level shifting stage, the drains of said PMOS differential input pair in communication with said differential current summing outputs, and where the sources of said PMOS differential input pair are in communication with each other;
• at least an NMOS differential input pair of transistors for current summing, where the gates of said NMOS differential input pair are coupled to said differential inputs, where the sources of said NMOS differential input pair are in communication with each other, and where the drains of said NMOS differential input pair are coupled to said differential current summing outputs;
• an output stage coupled to said differential current summing outputs to amplify signals of said differential current summing outputs, said output stage comprising diode-connected PMOS and NMOS transistors as the load for the positive and negative outputs of said output stage;
• and
• voltage sensing stages for low and high common mode input voltage sensing, said voltage sensing stages coupled to said output stage, said voltage sensing stage comprising switching means to activate said diode-connected PMOS transistors when said common mode input voltage is low and to activate said diode-connected NMOS transistors when said common mode input voltage is high.

13) A folded cascode receiver preamplifier with a CMOS rail-to-rail input, comprising:

• an open-loop high frequency differential amplifier having differential inputs and differential current summing outputs, said open-loop differential amplifier receiving at said differential inputs a common mode input voltage, where at a low common mode input voltage only PMOS transistors are active and at a high common mode input voltage only NMOS transistors are active, and where at a middle input common mode voltage, between said low and said high input voltage both PMOS and NMOS transistors are active, said open-loop high frequency differential amplifier further comprising:
• a level shifting stage comprising a transistor pair, said level shifting stage coupled to said differential inputs, said level shifting stage shifting the voltage level of said differential inputs;
• at least a PMOS differential input pair of transistors, where the gates of said PMOS differential input pair are coupled to the outputs of said level shifting stage, the drains of said PMOS differential input pair in communication with said differential current summing outputs, and where the sources of said PMOS differential input pair are coupled via resistive means with each other to improve the linearity of said PMOS differential input pair;
• at least an NMOS differential input pair of transistors for current summing, where the gates of said NMOS differential input pair are coupled to said differential inputs, where the sources of said NMOS differential input pair are coupled via resistive means with each other to improve the linearity of said NMOS differential input pair, and where the drains of said NMOS differential input pair are coupled to said differential current summing outputs;
• a low voltage sensing stage comprising a differential input pair for performing low common mode input voltage sensing when said common mode input voltage is low, where the gates of said differential input pair of said first voltage sensing stage are coupled to the outputs of said level shifting stage;
• a high voltage sensing stage comprising a differential input pair for performing high common mode input voltage sensing when said common mode input voltage is high, where the gates of said differential input pair of said first voltage sensing stage are coupled to said differential inputs;
• and
• an output stage coupled to said differential current summing outputs and providing an amplified output, said output stage having a negative and a positive load transistor stage, each comprising diode-connected PMOS and NMOS transistors coupled in parallel as the load for the negative and positive outputs of said output stage, respectively, and where outputs of said low and high voltage sensing stage couple to gates of control transistors in series with said diode-connected PMOS and NMOS transistors, respectively, of said negative and positive load transistor stage, whereby said voltage sensing stages activate said diode-connected PMOS and NMOS transistors of said negative and positive load transistor stage in correspondence with said PMOS and NMOS differential input pair of transistors.

26) A method of maintaining a constant voltage gain over a large common mode input voltage range for a high frequency receiver preamplifier with rail-to-rail capability, comprising the steps of:

• a) providing an open-loop differential preamplifier with PMOS and NMOS input transistor pairs and differential current summing outputs;
• b) coupling an output stage to said differential current summing outputs;
• c) activating PMOS and NMOS output transistors of said output stage via control means in correspondence with said PMOS and NMOS input transistor pairs;
• and
• d) keeping constant the ratio of the transconductance of said PMOS and NMOS output transistors divided by the transconductance of said PMOS and NMOS input transistor pairs.