Reducing device parasitics in switched circuits

A method of providing a sampling circuit comprising:

• providing a storage node configured to store a voltage across a memory element,
• providing a path from a first voltage to the storage node when a first MOS transistor is “ON,”
• providing a path from a third voltage to a bulk of the first MOS transistor when a third MOS transistor is “ON,” and
• floating the bulk of the first MOS transistor when the third MOS transistor is “OFF,” wherein an effective parasitic capacitance of the first MOS transistor is reduced during a sample phase.

A method of providing a sampling circuit comprising:

• providing a storage node configured to store a voltage across a memory element,
• providing a path from a first voltage to the storage node when a first MOS transistor is “ON,”
• providing a path from a second voltage to the storage node when a second MOS transistor is “ON,”
• providing a path from a third voltage to a bulk of the first MOS transistor through a first large resistance, and
• providing a path from a fourth voltage to a bulk of the second MOS transistor through a second large resistance, wherein
• an effective parasitic capacitance of the first MOS transistor is equal to a series combination of its Cj plus its Cw, and
• an effective parasitic capacitance of the second MOS transistor is equal to a series combination of its Cj plus its Cw.

A sampling circuit comprising:

• a storage node configured to store a voltage across at least one memory element,
• a first MOS transistor configured to provide a path from a first voltage to the storage node when the first MOS transistor is “ON,”
• a second MOS transistor configured to provide a path from a second voltage to the storage node when the second MOS transistor is “ON,”
• a third MOS transistor configured to provide a path from a fifth voltage to the storage node when the third MOS transistor is “ON,”
• a fourth MOS transistor coupled to a second end of the at least one memory element, configured to provide a path from a sixth voltage to the second end of the at least one memory element when the fourth MOS transistor is “ON,”
• a fifth MOS transistor configured to provide a path from a seventh voltage to a bulk of the fourth MOS transistor when the fifth MOS transistor is “ON,” and to float the bulk of the fourth MOS transistor when the fifth MOS transistor is “OFF,” wherein
• an effective parasitic capacitance of the fourth MOS transistor is reduced when the fifth MOS transistor is “OFF,” and
• the bulk of the fourth MOS transistor is periodically refreshed.

A differential sampling circuit comprising two parallel paths, each parallel path comprising:

• a storage node configured to store a voltage across at least one memory element,
• a first MOS transistor configured to provide a path from a first voltage to the storage node when the first MOS transistor is “ON,”
• a second MOS transistor configured to provide a path from a second voltage to the storage node when the second MOS transistor is “ON,”
• a third MOS transistor configured to provide a path from a fifth voltage to the storage node when the third MOS transistor is “ON,”
• a fourth MOS transistor coupled to a second end of the at least one memory element, configured to provide a path from a sixth voltage to the second end of the at least one memory element when the fourth MOS transistor is “ON,”
• a fifth MOS transistor configured to provide a path from a seventh voltage to a bulk of the fourth MOS transistor when the fifth MOS transistor is “ON,” and to float the bulk of the fourth MOS transistor when the fifth MOS transistor is “OFF,” wherein
• an effective parasitic capacitance of the fourth MOS transistor is reduced when the fifth MOS transistor is “OFF,” and
• the bulk of the fourth MOS transistor is periodically refreshed.