Latch with clocked devices

A semiconductor device comprising:

• a mechanical package;
• and
• a semiconductor die comprising:
• a semiconductor layer,
• a plurality of metal layers,
• a clock distribution network that distributes a clock signal within the die, and
• a latch circuit comprising:
• a feed-forward circuit comprising:
• a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device with gate driven by a source clock signal, and wherein the source clock signal is derived from the clock signal,
• a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device with gate driven by the source clock signal, and wherein the first output is operatively connected to the second input,
• a keeper circuit operatively connected to the first output, wherein the keeper circuit is driven from the second output, and
• a feed-back circuit comprising:
• a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output,
• a fourth-inverting-stage with a fourth input and a fourth output, wherein the fourth input is operatively connected to the third output, and wherein the fourth output is connected to the third input to form a storage node,
• wherein the latch circuit consists of no more than four clocked devices that switch with the source clock signal.

A system comprising:

• an input device;
• an output device;
• a mechanical chassis;
• a printed circuit board;
• and
• a semiconductor device comprising:
• a mechanical package, and
• a semiconductor die comprising:
• a semiconductor layer,
• a plurality of metal layers,
• a clock distribution network that distributes a clock signal within the die, and
• a latch circuit comprising:
• a feed-forward circuit comprising:
• a first-inverting-stage with a first input and a first output, wherein the first-inverting-stage comprises a first clocked device with gate driven by a source clock signal, and wherein the source clock signal is derived from the clock signal,
• a second-inverting-stage with a second input and a second output, wherein the second-inverting-stage comprises a second clocked device with gate driven by the source clock signal, and wherein the first output is operatively connected to the second input,
• a keeper circuit operatively connected to the first output, wherein the keeper circuit is driven from the second output, and
• a feed-back circuit comprising:
• a third-inverting-stage with a third input and a third output, wherein the third input is operatively connected to the second output,
• a fourth-inverting-stage with a fourth input and a fourth output, wherein the fourth input is operatively connected to the third output, and wherein the fourth output is connected to the third input to form a storage node,
• wherein the latch circuit consists of no more than four clocked devices that switch with the source clock signal.