CMOS Clock Receiver with Feedback Loop Error Corrections

A clock receiver comprising:

• a differential amplifier having inputs for a pair of differential clock signals;
• a duty cycle error detector having inputs for a pair of amplified differential clock signals and an output for a duty cycle error correction signal;
• and
• a signal conditioner, provided within the differential amplifier, having an input for the duty cycle error correction signal, the signal conditioner to adjust the differential clock signals in response to the duty cycle error correction signal.

A method to correct duty cycle errors and cross point errors in a clock receiver, comprising:

• amplifying a pair of differential clock signals;
• detecting duty cycle errors of the differential clock signals and generating a duty cycle error correction signal therefrom;
• detecting cross point errors of the differential clock signals and generating a cross point error correction signal and
• adjusting, as part of the amplifying, the differential clock signals according the duty cycle error correction signal and cross point error correction signal.

A clock receiver comprising:

• a differential amplifier having inputs for a pair of differential clock signals;
• a duty cycle error detector having inputs for a pair of amplified differential clock signals and an output for a duty cycle error correction signal;
• a cross point error system having inputs for the pair of amplified differential clock signals and an output for a cross point error correction signal;
• a signal conditioner, provided within the differential amplifier, having inputs for the duty cycle error correction signal and the cross point error correction signal, the signal conditioner to adjust the differential clock signals in response to the duty cycle error correction signal and the cross point error correction signal.