Decoder circuit
AssigneeRenesas Technology Corp.
InventorsMitsuhiro TOMOEDA, Makoto Muneyasu, Masahiro Hosoda
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AssigneeRenesas Technology Corp.
InventorsMitsuhiro TOMOEDA, Makoto Muneyasu, Masahiro Hosoda
Estimating the term…
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
1-4. (canceled)
A decoder circuit which defines selection/non-selection of an object to be controlled with an output signal, the decoder circuit comprising:
Dependencies are inferred from the claim text.