US 2010/0301900 A1Published application

Pre-Charged High-Speed Level Shifters

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorKuo-Liang Deng

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Abstract

An integrated circuit structure includes a latch having a first output node and a second output node complementary to each other. A first pre-charge transistor has a source-drain path coupled between a positive power supply node and the first output node. A second pre-charge transistor has a source-drain path coupled between the positive power supply node and the second output node. The integrated circuit structure further includes a delay-inverter coupled between a signal input node and inputs of a first NMOS transistor and a second NMOS transistor in the latch. The delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor.

Claims20

Dependent claims

An integrated circuit structure comprising:

a first positive power supply node carrying a first positive power supply voltage;
a second positive power supply node carrying a second positive power supply voltage higher than the first positive power supply voltage;
a signal input node;
a latch comprising:
a first output node and a second output node complementary to each other;
a first PMOS transistor and a first NMOS transistor with drains coupled to the first output node;
and
a second PMOS transistor and a second NMOS transistor with drains coupled to the second output node;
a first pre-charge transistor comprising a source-drain path coupled between the second positive power supply node and the first output node;
a second pre-charge transistor comprising a source-drain path coupled between the second positive power supply node and the second output node;
and
a first delay-inverter coupled between the signal input node and inputs of the first NMOS transistor and the second NMOS transistor, wherein the first delay-inverter is configured to allow one of the first pre-charge transistor and the second pre-charge transistor to pre-charge a respective one of the first output node and the second output node before an input signal at the signal input node arrives at a gate of a respective one of the first NMOS transistor and the second NMOS transistor.

9 more elements

An integrated circuit structure comprising:

a latch comprising:
a first output node and a second output node complementary to each other;
a first PMOS transistor and a first NMOS transistor with drains coupled to the first output node;
and
a second PMOS transistor and a second NMOS transistor with drains coupled to the second output node, wherein sources of the first NMOS transistor and the second NMOS transistor are connected to a VSS node;
a first pre-charge transistor comprising a source-drain path coupled between a first positive power supply node and the first output node;
a second pre-charge transistor comprising a source-drain path coupled between the first positive power supply node and the second output node;
a plurality of inverters coupled in series and comprising:
a first inverter comprising a first input coupled to a gate of the first pre-charge transistor and a first output coupled to a gate of the second pre-charge transistor;
and
a last inverter comprising a second input coupled to a gate of the first NMOS transistor and a second output coupled to a gate of the second NMOS transistor;
a third NMOS transistor comprising a drain connected to the first output node, a gate connected to the second output node, and a source connected to a first non-VSS node;
and
a fourth NMOS transistor comprising a drain connected to the second output node, a gate connected to the first output node, and a source connected to a second non-VSS node.

11 more elements

Dependencies are inferred from the claim text.