High impedance, high parallelism, high temperature memory test system architecture

Abstract

An electronic device for use with a probe head in automated test equipment includes first and second pluralities of semiconductor devices. The first plurality of semiconductor devices is arranged to form at least one driver arranged to couple to a device under test. The at least one driver is configured to transmit a signal to the at least one device under test. The second plurality of semiconductor devices is arranged to form at least one receiver arranged to couple to the device under test. The at least one receiver is configured to receive a signal from the at least one device under test. Each of the second plurality of semiconductor devices has a thickness less than about 300 μm exclusive of any electrical interconnects. The at least one receiver is adapted to mount directly to the probe head.

Dependencies are inferred from the claim text.