Structure and Method for Power Field Effect Transistor
AssigneeTexas Instruments Incorporated
InventorSreenivasan K. KODURI
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AssigneeTexas Instruments Incorporated
InventorSreenivasan K. KODURI
Estimating the term…
A packaged semiconductor device has a metal plate (1200) with sawed sides (1200c), a flat first surface (1200a) and a parallel second surface (1200b); the plate is separated into a first section (1201) and a second section (1202) spaced apart by a gap (1230). The plate has on the second surface (1200b) at least one insular mesa (1205) of the same metal in each section, the mesas raised from the second plate surface. The device further has an insulating member (1231), which adheres to the first plate surface, bridges the gap, and thus couples the first and second sections together. The device further has a vertical stack (1270) of two power FET chips (1210) and (1220), each having a pair of terminals on the first chip surface (1211 and 1212; 1221 and 1222 respectively) and a single terminal on the second chip surface. The single terminals of chip (1210) and chip (1220) are attached to each other to form the common terminal (1240). The terminal pair (1221) and (1222) is conductively attached to plate (1200) so that terminal (1221) contacts the first plate section (1201) and terminal (1222) contacts the second plate section (1202). The terminal pair (1211) and (1212) is available for attachment to a substrate.
An apparatus comprising:
An apparatus comprising:
An apparatus comprising:
A method for fabricating an apparatus comprising the steps of:
A method for fabricating an apparatus comprising the steps of:
A method for fabricating an apparatus comprising the steps of:
A method for fabricating a metal plate comprising the steps of:
Dependencies are inferred from the claim text.