Silicon-Based Thin Substrate and Packaging Schemes
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSzu Wei Lu, Clinton Chao, Ann Luh, Tjandra Winata Karta, Jerry Tzou, Kuo-Chin Chang
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Abstract
A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.
Claims20
A semiconductor package assembly comprising:
- a silicon-based package substrate having a thickness of less than about 200 μm;
- a semiconductor chip comprising at least one low-k dielectric layer having a k value of less than about 3.0;
- a plurality of solder bumps interposed between the semiconductor chip and a first surface of the silicon-based package substrate;
- a plurality of under bump metallizations formed on a first surface of the silicon-based package substrate disposed to receive the plurality of solder bumps and forming an outer perimeter;
- a plurality of BGA balls overlying the first surface of the silicon based package substrate;
- and
- a plurality of conductive traces disposed on the silicon-based substrate each having a horizontal portion and each coupling at least one of the under bump metallizations to at least one of the BGA balls.
A semiconductor package assembly comprising:
- a silicon-based package substrate;
- a semiconductor chip over the silicon-based package substrate, wherein the semiconductor chip comprises at least one low-k dielectric layer having a k value of less than about 3.0;
- a plurality of solder bumps coupling the semiconductor chip and the silicon-based package substrate, wherein the plurality of solder bumps has a lead concentration substantially less than about five percent;
- a plurality of under bump metallizations disposed on a first surface of the silicon-based package substrate to receive the plurality of solder bumps, the plurality of under bump metallizations forming an outer perimeter, each under bump metallization coupled to a metal trace on the silicon-based package substrate having a horizontal portion;
- and
- a plurality of BGA balls overlying the first surface of the silicon based package substrate;
- each disposed outside the outer perimeter and coupled by one of the metal traces to at least one of the under bump metallizations.
A silicon-based package substrate comprising:
- a plurality of BGA balls disposed on a first surface of the silicon based package substrate;
- a plurality of under bump metallizations formed on the first surface of the silicon based package substrate and forming an outer perimeter inside the plurality of BGA balls;
- and
- a plurality of metal traces disposed on the silicon based package substrate and having a horizontal portion, connected to the under bump metallizations and the BGA balls, wherein the silicon-based package substrate has a thickness of less than about 200 μm and contains greater than about 40 percent silicon.
Dependencies are inferred from the claim text.