High-Voltage BJT Formed Using CMOS HV Processes

An integrated circuit device comprising:

• a semiconductor substrate;
• a high-voltage bipolar junction transistor comprising:
• a plurality of base unit cells, each comprising:
• a first heavily doped region of a first conductivity type;
• and
• a first insulation region in the semiconductor substrate and encircling the first heavily doped region;
• a plurality of emitter unit cells, each comprising:
• a second heavily doped region of a second conductivity type opposite the first conductivity type;
• and
• a second insulation region in the semiconductor substrate and encircling the second heavily doped region;
• a plurality of collector unit cells, each comprising:
• a third heavily doped region of the second conductivity type;
• and
• a high-voltage well region of the second conductivity type underlying and contacting the third heavily doped region, wherein the plurality of base unit cells, the plurality of emitter unit cells, and the plurality of collector unit cells are arranged as an array with rows and columns;
• a buried layer of the second conductivity type in the semiconductor substrate and having a top surface contacting a bottom surface of the high-voltage well region;
• and
• well regions of the first conductivity type between and adjoining the first heavily doped region and the buried layer, and between and adjoining the second heavily doped region and the buried layer.

An integrated circuit device comprising:

• a semiconductor substrate;
• and
• a high-voltage bipolar junction transistor comprising:
• an insulation region comprising a plurality of horizontal strips, and a plurality of vertical strips intersecting the plurality of horizontal strips, wherein the plurality of horizontal strips and the plurality of vertical strips are arranged in a periodical pattern;
• a plurality of base contacts of a first conductivity type, each at a cross-section of one of the plurality of horizontal strips and one of the plurality of vertical strips, wherein each of the base contacts is encircled by the insulation region;
• a plurality of collectors, each comprising:
• a first heavily doped region of a second conductivity type opposite the first conductivity type;
• and
• a high-voltage well region of the second conductivity type underlying and contacting the first heavily doped region;
• a plurality of emitters, each comprising a second heavily doped region of the second conductivity type, wherein each of the plurality of emitters and each of the plurality of collectors are laterally separated apart from others by the insulation region;
• and
• a buried layer of the second conductivity type in the semiconductor substrate and having a top surface contacting a bottom surface of the high-voltage well region.